资源列表
AnumberrT
- AT89S52控制64*16双基色点阵led显示数字数字通过过自摸取出数组8*16硬件环境：595，AT89S52,138 -AT89S52 control 64* 16 dual color dot matrix led display digit number by Zimo remove an array of 8* 16 Hardware Environment: 595, AT89S52 is, 138
L16-32_1820-1e
- 16_32的led多功能点阵具有温度度采集_18b20实时时钟_ds1302 -16_32 led multi-function lattice has a temperature of collection _18b20 real-time clock _ds1302
Ndianzhengunde
- 点阵显示新历 温度滚动,自己写的通俗易懂，有C语语言基础的都可以看懂 ，经测试可直接使用。 -The dot matrix display the history of the new temperature scroll, written in easy to understand, in C language based can understand, has been tested and can be used directly.
116128LEDDS136
- 16128的LED点阵，程序和原则的地图平， DDs1302 18 B20,可以直接使用。 -16128 dot matrix LED, procedures and principles of map level, DDs1302 18 B20, can be used directly.
1dappinmu16XX6
- 大屏幕16X64LED点阵滚动显示出来来 大屏幕16X64LED点阵滚动显示出来 -Large screen 16X64LED lattice scroll out to the big screen 16X64LED lattice scroll displayed
kMMyycousee
- keilc51写的，双色LLED点阵屏 可移动 速度可调 -keilc51 write, color LLED lattice screen removable adjustable speed
A158883834166b
- 关于16行64列的LED点阵，能够左右移动，程序源码简简单易懂易懂，希望大家来下载 可直接使用。 已通过测试。 -About 16 rows of 64 LED dot matrix, be able to move around the program source code, the simple and easy to understand and easy to understand, want to download can be used directly. Has been t
MDB_Version_4-2
- mdb协议，包含各种终端，自动售货机协议-Version 4.1 of this specification is the fifth release of the international Multi-Drop Bus/ Internal Communication Protocol (MDB/ICP).
pplllrarl
- 用VHDL写的数字锁相环程序源码 pll.vhd为源文文件 pllTB.vhd为testbench 可直接使用。 -Written using VHDL digital PLL pll.vhd program source code for the source text file pllTB.vhd testbench can be used directly.
ffirr_166i
- fir低通滤波器 用于dspbuilder pll：25nss data 400khz sin 10.8khz 已通过测试。 -fir low pass filter for dspbuilder pll: 25nss data 400khz sin 10.8khz has been tested.
FdplllzipP
- ＦＰＧＡ实现全数字锁相环，运用硬件描述评议议verilog HDL，顶层文件ＤＰＬＬ．Ｖ -FPGA implementation of DPLL, the use of hardware descr iption council meeting Verilog HDL top-level file DPLL is. V
sfdppllli
- 简单易懂的可配置dpll的VHDL代码。用于时钟恢复后的相位抖动的的滤波有非常好的效果， 而且能参数化配置pll的级数。 已通过测试。 -Straightforward configuration VHDL code dpll. Very good results for the clock recovery phase jitter filtering, and can be parameterized configuration pll series. Has been tested.