资源列表
Oalttclkloockc
- 倍频锁频，VHDL程序源码，运行正确确，可修改性强，最优处理 -Multiplier locked, VHDL program source code, run the correct indeed, can modify the strong, the optimal treatment
Othrreediv_ccd
- 奇数分频与倍频，只需修改参数数就能实现较难的基数分频与倍频 -Odd divider and multiplier, simply modify the parameter number will be able to achieve the difficult base divider and multiplier
LlcddtvvC
- 调试好的LCDTVV方案，新款的，有价值 -Good debugging LCDTVV program, the new, valuable
Solution_19
- This solution would help to study controller design. Especially Buck converter.
VHDL-Cookbook
- VHDL is a language for describing digital electronic systems. It arose out of the United States Government’s Very High Speed Integrated Circuits (VHSIC) program, initiated in 1980. In the course of this program, it became clear that there was a
FPGA_VHDL_Clock
- 利用QuartusII VHDL硬件描述语言写的一枚简单的小时钟，具有设定闹钟，设定时间，设定闹钟长度的功能-The QuartusII the VHDL hardware descr iption language used to write a simple little clock set the alarm, set time, set the alarm clock the length of the function
Aid
- this for usb high speed chip ft232h ic from ftdichip.com download and can used certainly.-this is for usb high speed chip ft232h ic from ftdichip.com download and can used certainly.
MVHDDLzipa
- 曼彻斯特编码的VHDL源程序源码?
cvvhhdl_vgao
- 彩条信号发生器使用说明使用模块有：VGA接口、脉冲沿模块、时钟源模块。 使用步骤：1.打开电源+5V2.信号连接，按下表将1K30信号与实际模块连接好。3.1K30板板连接好并口线，并将程序源码加载。4.将将彩色显示出来器的线与VGA接口连接好。5.彩条信号就能在显示出来器中产生，通过脉冲沿模块按键MS1能改变产生彩条的 可直接使用。 -The color bar signal generator using the module: VGA interface, the pulse alon
urunn_length_s
- <p>用verilog 开发应用于图像压缩编码中使用行程长度编码(run lengthencoding，RLE)对交流系数(Aa)进行编码。</p> -<p> With verilog development for image compression using run length encoding (run lengthencoding, RLE) coding to encode the exchange coefficient (Aa). <
51
- 51单片机电子钟程序 （采用调用显示子程序以改善LED的显示闪烁现象）-51 MCU clock program (call display routines to improve the LED display flicker)
cnt24
- 24进制计数器，实现了电子时钟小时位的24进制计数-24 hex counter