资源列表
Desktop.tar
- I ve implemented what oi believe to be a very usefull and easy way to understand the FIFO queue using a DPRAM
3-3-median-filter
- verilog编写的适用于fpga的3x3模板中值滤波-verilog fpga prepared for the 3x3 median filter template
Code_for_MedianFilter33
- 包含边缘探测的中值滤波FPGA工程，分辨率1024x16-Contains the edge detection filter in the value of the FPGA project
VGA-controller
- 本示例演示了VGA的控制方法，程序配置后可以在CRT上显示 -This example demonstrates the VGA control method, the program can be configured to display in the CRT
V35interface-communicate
- V.35接口与E1接口之间转换的基本原理,介绍了E1信道分时隙通信的基本过程，叙述了基于FPGA用VHDL和QuartusII来仿真本系统设计与实现的过程。-V.35 interface and E1 interface to convert between the basic principles of E1 channel introduces the basic process of communication sub-time slot, described by VHDL and FP
ROM
- Verilog sine的查找表，相信大家会用到-Verilog sine lookup table, I believe we will use
stepmotor-paper-
- 基于 FPGA 设计的步进电机控制系统 -FPGA-based stepper motor control system design
encoder_interface
- 正交编码器接口 用于正交四倍频电路 伺服驱动器常用-Quadrature Encoder Interface circuit for quadrature servo drives commonly used frequency
e2rom
- eeprom的verilog程序，用过，很好用。个人修改后直接调用-eeprom of verilog program, used, very good use. Personal modified to directly call
lab9_0~60
- 顯示0~60的循環數,可顯示在SEG上方!-Showing 0 to 60 cycles, SEG can be displayed in the top!
verilog-study
- VERILOG HDL的入门学习资料，对于想进一步学习FPGA的朋友有一定的帮助。-VERILOG HDL entry-learning materials, for those who want to learn more FPGA' s friends have some help.
DS18B20
- 用VHDL写的DS18B20程序，用注解，非常实用-DS18B20 written with VHDL program, with comments, very useful ~ ~ ~