资源列表
DDR2PTiming
- 用Xilinx ip core 生成器所产生的DDR2控制器，进行时序分析代码-Xilinx ip core generator a ddr2 controllor time analysis
61EDA_H363
- 基于xilinx spantan3E开发板的20个例程-Xilinx spantan3E development board based on the 20 routines
design0
- verilog coding for basic gates
design1
- verilog code for some adders
design2
- verilog code for some multiplexers
Printer
- The internal circuit of the simulated printer module, in a students course design - A parallel output controller (POC) .-The internal circuit of the simulated printer module, in a students course design - A parallel output controller (POC) .
fh_ram_s_w_r_16_512
- 单口串行可读写16x512的ram的verilog源代码-singal serial writeable and readable 16x512 ram
huwei--about-verilog-teach
- 华为出品 关于verilog的非常完美教程 对于从事verilog编程者很有帮助-Huawei produced the perfect tutorial on verilog verilog programmers engaged in useful
The-Speedy-DDR2-Controller-
- The Speedy DDR2 Controller For FPGAs ERSA 2009 Final
CycloneII
- CycloneII器件数据手册，搞FPGA开发的工程师可以学习下，-CycloneII device data sheet, FPGA development engineers can engage in learning, the
8X8LED_verilog_fpga
- 8*8的LED 用VERILOG 写的FPGA，程序，这可是用在最近的项目中，下载用在最近的项目中，请标明出处！-8* 8 LED written with VERILOG FPGA, procedures, and this is used in a recent project, download used in recent projects, please credit!
stopwatch
- 这个程序是用verilog语言编写的秒表的小程序，可以精确到秒，有具体的程序，在开发板上实验成功！-This program is written in verilog stopwatch with a small program that can accurately to the second, there are specific procedures, the development board experiment is successful!