资源列表
altiumPdesigner3
- 基于NB板的FPGA的开发与应用。。。Altium 公司出厂自带的-NB DEVELOP
cpu-design
- VHDL设计的一个可综合的精简指令集的CPU，加上外围模块，类似与51单片机，当然还缺少很多功能，只是雏形，供大家交流-VHDL design of an integrated RISC CPU, coupled with external modules, exhausted and 51 single-chip, of course, the lack of many features, but prototype for all to share
impuls
- for QUARTUS 2.0 and more. Synchronous Detector Pulses
one_bit_cpu
- one bit CPU AHDL QUARTUS 2.0 and more
VHDL-translation-in-Russian
- VHDL translation in Russian
Lab07_DigitalLock
- Design and Implementation of a vhdl based Digital Lock
FPGA-IIC
- 利用VHDL实现延时程序 很不错的资料 适合学习CHDL-Delay procedure using VHDL implementation very good information for learning CHDL
Fenpin
- 基于VHDL语言时钟晶振48Mhz的分频器的制作能够实现1HZ分频的时钟信号。-48Mhz clock oscillator based on VHDL language to achieve the production of crossover frequency of the clock signal 1HZ.
Jshuqi
- 基于VHDL原理图实现的计数器 时钟晶振为48MHZ -Schematic-based VHDL implementation of the counter clock oscillator is 48MHZ
1122
- 已经成功的FPGA 控制的SDRAM控制器代码.只要修改你需要的宽度-FPGA has been successfully controlled by SDRAM controller code. As long as you need to modify the width of
0011
- Altera_Sdram_IP_源码 可以参考的-Altera_Sdram_IP_ source for reference
Qdaqi
- 基于VHDL语言 实现八路抢答器 有源时钟48mhz 功能为任意按键按下屏蔽其它按键输入-VHDL language based on the active clock 48mhz eight Responder function to any button is pressed the other key input screen