资源列表
LED_7seg
- FPGA的7段数码管程序，用verilog编写，很好的程序，不要错过啊-The 7-segment FPGA program written with verilog, very good program, do not miss ah
ModelSimjiaocheng
- modelism中文教程，描述了一个字节选择器的编程-modelism Chinese tutorial describes the programming of a byte selector
key_scan4X4
- 基于ＦＰＧＡ设计的矩阵键盘经过多次测试非常的好用 ＶＨＤＬ语言-FPGA-based design of repeated testing matrix keyboard is very easy to use VHDL language
LCD1602shizhong
- 基于FPGA设计的1602显示的时钟，分为几个模块，VHDL语言-FPGA-based design 1602 show the clock, is divided into several modules, VHDL language
LCD2864
- 基于FPGA设计的驱动12864让其显示-FPGA-based design-driven display it 12864
fir
- this is an vhdl code for fir filter-this is an vhdl code for fir filter....
VHDL-for-PLL.doc
- vhdl code for phase locked loop
VHDL_TipsTricks
- tips to design fir filter step by step
Cyclone-FPGA-Family-Data-Sheet
- Cyclone FPGA Family 数据手册。讲述altera公司的FPGA的相关器件。主要用于选型。-Cyclone FPGA Family Data Sheet. Altera about the company' s FPGA-related devices. Mainly used for selection.
reed3_ise10migration
- reed solomon encoder
AES-algorithm-design
- 基于FPGA的AES算法芯片设计实现,文中具体给出了测试的运行时间等数据-AES algorithm for FPGA-based chip design to achieve
open8_urisc_latest.tar
- opencores urisc code