资源列表
caideng
- 这个程序是用verilog语言编写的彩灯的小程序，使用状态机来实现，可以实现多种花型，有具体的程序！-This program is written in verilog small lantern, the use of state machine, you can achieve a variety of flowers, there are specific procedures!
chuzuche
- 本程序使用verilog语言编写的出租车计价系统，实现时距并计！主要用状态机来实现！-This program uses the taxi meter verilog language system, and taking into account the time-distance! State machine is mainly used to achieve!
yinliao
- 本程序采用verilog语言编写实现仿真自动饮料机的功能，采用状态机来实现！-This procedure uses verilog language automatic beverage machine emulation capabilities, the use of state machine!
jiaotongdeng
- 本程序采用verilog语言实现交通灯的模拟，很有实用价值！有具体的程序！-This procedure uses verilog language simulation of traffic lights, very practical! Has a specific program!
1
- 基于VerilogHDL的DDS设计与仿真论文-The DDS-based design and simulation VerilogHDL Papers
FIR-FPGA
- 一种基于FPGA的高效FIR滤波器的设计与实现 -An efficient FIR filter based on FPGA of design and implementation
SystemVerilog-for-Verification--2nd-Ed
- This a system verilog book.-This is a system verilog book.
CANCS
- 用的是able语言 编写的一段程序 可以参考学习使用-Is able to use a program written in a language can refer to learn to use
cpu
- 设计一个简化的处理器（字长8位），并使其与内存MEM连接，协调工作。用VHDL以RTL风格描述。该处理器当前执行的指令存放在指令寄存器IR中。处理器的指令仅算逻指令和访问内存指令）。-Design a simplified processor (8-bit word length), and connect it with the memory MEM, and coordination. Described with VHDL in RTL style. The processor is c
CRC
- Cyclic redundancy check code (16-bit) Very good code verified code
rs_231_modified
- Reed solomon codes (231 message information)
rsa.tar
- good working RSA code with testbench