资源列表
3
- FIR数字滤波器的优化与验证 -FIR digital filter optimization and verification FIR digital filter optimization and verification
TV
- an analog video input to VGA video output Verilog
Ex11_LCD1602
- FPGA LCD1602 VDHL源码-FPGA LCD1602
DVIaVGA
- 鉴于大家对两者的误解，有必要说明VGA与DVI的根本区别-Given all of the misunderstanding between the two, it is necessary that the fundamental difference between VGA and DVI
Taxi_meter
- 设计一个满足日常生活所需功能的出租车计费器，实现计费功能。-Designed to meet the daily needs of a taxi meter function and achieve billing functions.
Crack_QII72
- QuartusII7.2破解文件注册文件-QuartusII7.2 crack file registration documents
FIFO
- Quartus下VHDL编写的一个FIFO模块，调试于c6000系列。控制Cache输入输出数据-A FIFO module in VHDL Quartus, commissioning c6000 series
dianziqin
- 简易电子琴的制作，包括自动播放功能和基本琴键，占空比50 -The production of simple keyboard, including the AutoPlay feature keys, 50 duty cycle
ASM
- 时序逻辑电路的系统设计方法介绍,适合大部分人的EDA学习-System design sequential logic circuit descr iption, suitable for most people to learn EDA
UARTofVHDL
- 基于vhdl的uart程序设计：完全按照论文格式编写。-The uart vhdl-based Programming: paper format exactly as written。
clock
- fpga实现电子时钟在数码管上显示，有设置时间功能。显示时分秒。-fpga electronic clock on the digital display, set the time function. Displayed every second.
qudou
- 去抖电路的简单代码，具有很好的移植性-To shake the simple circuit code, has the very good portability......