资源列表
fpu_v19
- 浮点数运算的VHDL代码实例，实现CPU浮点运算-failed to translate
digital-clock
- 基于FPGA的数字时钟设计，时钟可以按设定好的时间进行自动计时，FPGA板子上可以显示相应的时钟数字，是数字电路课程的一个课程设计，也是对于VHDL语言的一个熟悉过程.-FPGA-based digital clock design, the clock can be a good time to set automatic timing, FPGA board clock can display the corresponding figure is a digital circuit des
DM1_KEYs_LEDs_C5H
- 在FPGA中的 cycloneII 中实现键盘控制的顶层实体设计以及相关功能设计，经过试验编译成功并可以运行的程序-In FPGA cycloneII keyboard control to achieve top-level physical design and design-related functions, tested and successfully compiled programs can run
jiafaqi
- quartusii软件仿真实验代码 十进制加法计数器-quartusii software simulation code decimal addition counter
SRAM_WR
- 实现对SRAM的读写。具体功能：在DE2开发板上通过键盘SW0-SW3输入数据存入SRAM中，同时LEDR0=LEDR3显示输入数据；SW17控制SRAM的输入与读出，LEDR4-LEDR7显示读出结果。-To achieve the SRAM read and write. Specific features: In the DE2 development board via the keyboard SW0-SW3 input data into the SRAM, while LEDR0
Verilog_HDL_PIC16c5x.zip
- 完整的PIC16系列单片机verilog描述,A complete descr iption of PIC16 series of microcontrollers verilog
vhdlcpld.rar
- 用vhdl实现四人智能抢答器，强大成功，显示抢答号。超时没有人回答，有报警提示。,Using vhdl implementation of four smart Responder, strong success, showing to answer in number. Out that no one answered, there is alarm.
v39-23
- Theory of designing adder/substracter by VerilogHDL
adc_dac_demo
- 在FPGA芯片上进行AD采集应用开发的良好例程-AD collection good routine application development on the FPGA chip
200558080220
- 基于VHDL的自动售货机设计,希望对大家有点帮助
Crack_QII72
- 对于quartus 7.2软件进行破解的工具保-For quartus 7.2 crack tools software security
rs_encode
- rs纠错编码及原理及其实现方法,及相关程序代码-rs encode theory and method； relevant codes as well