资源列表
danzhouqiCPU
- VHDL单周期CPU设计,基于Quartus II 开发平台-VHDL single-cycle CPU design, Quartus II development platform based on
FPGAbasic
- FPGA入门基础教程，以实践为基础，适合具备基本的数字电路设计基础的初学者-FPGA Started Essentials, based on practice, suitable for digital circuit design with the basic foundation for beginners
verilog
- 关于数字系统设计的Verilog教程，是一本既有理论又有实践的设计大全。-Verilog digital system design on the tutorial, is a theoretical and practical design both Daquan.
uartTransceiver
- Verilog Serial port
sr_flipflop
- sr_flipflop verilog model
seven_segment
- 7segment verilog module
decoder
- 3_8decoder verilog module
signed_mul
- signed multiplication verilog module
watch(2)
- digital watch : verilog source code
stopwatch1
- stopwatch : verilog source code
ffj
- 使用硬件语言实现分接，使用QUARTUS2软件仿真测试-Tap hardware language, the use of simulation testing QUARTUS2
div_n_0_5
- 使用verilog实现任意奇数n+0.5分频，使用ise11.1和modelsim se6.5仿真测试-Using an arbitrary odd number n+0.5 verilog divide, the use of simulation testing ise11.1 and modelsim se6.5