资源列表
VGA_driver_verilog
- 基于Verilog HDL的VGA驱动程序设计-Based on Verilog HDL design of the VGA driver
DAQmx-Pulse-Train-Frequency
- daq frecuency pwm labview
VHDL-Verilog-Systemverilog
- 解决初学者疑惑：VHDL、Verilog，System+verilog比较,适合初学者对三种语言的理解-Solve beginners doubt: VHDL, Verilog, the System+ Verilog, suitable for beginners understanding of the three languages
2
- VHDL描述的电子时钟VHDL程序与仿真，可以验证。-VHDL procedure described in VHDL and simulation of electronic clock, can be verified.
vhdlcoder
- 本文件夹包含了16个VHDL 编程实例，仅供读者编程时学习参考。 一、四位可预置75MHz -BCD码（加/减）计数显示器（ADD-SUB）。 二、指示灯循环显示器（LED-CIRCLE) 三、七人表决器vote7 四、格雷码变换器graytobin 五、1位BCD码加法器bcdadder 六、四位全加器adder4 七、英语字母显示电路 alpher 八、74LS160计数器74ls160 九、可变步长加减计数器 multicount 十、可
PULSEWIDTH
- 一个关于脉冲宽度的VHDL实例，对于VHDL语言的学习者很有帮助。-Pulse width on the VHDL example, the VHDL language learners helpful.
dianzizhong
- 电子时钟程序设计与仿真验证，VHDL语言-Clock Electronics Design and Simulation, VHDL language
eight-gated-lock
- 智能八位门控密码锁 可以实现自行设计密码 密码正确 门控电路开启 密码错误 报警电路响起-Microcontroller-based eight-gated lock Can design their own password Gating circuit is opened the password is correct Sounded the alarm circuit password is wrong
ThesummaryofSoCOCB
- 随着以IP核复用为基础的SoC设计技术的发展，工业界及研究组织积极从事相关IP互联标准 方案的制定工作，从目前的研究和发展看，影响力较大的有IBM 公司的CoreConnect、ARM 公司的AMBA 和Silicore Corp公司的Wishbone。基于现有IP互联接口标准技术的发展现状，本文对这三种SoC总线技 术进行了详细介绍。-Along with the IP core reuse-based SoC design technology, industry and res
VHDL-LED
- 设计一个带计数使能、异步复位、带进位输出的增1六位二进制计数器，计数结果由共阴极七段数码管显示-Design a counter with enable and asynchronous reset, brought by a six-bit output of the binary counter, counting the results from the common cathode seven segment display
Comparison
- VHDL，verilog and SystemVerilog的优缺点说明-Comparison of VHDL, Verilog and SystemVerilog.pdf
usb1_funct_latest.tar
- USB 1.1 slave/device IP core. Default configuration is 6 endpoints: 1 Control, 1 Isochronous IN, 1, Isochronous Out, 1 Bulk IN, 1 Bulk Out, 1 Interrupt IN. Includes control engine, providing full enumeration process in hardware - no external mi