资源列表
jiaotongdeng
- 交通灯的VHDL程序，实现在十字路口的交通灯的控制。简单易懂，硬件能够实现。-VHDL procedures for traffic lights to achieve at the crossroads of traffic lights control. Easy to understand, the hardware can be achieved.
SECOND
- 基于FPGA的VERILOG的一秒亮一个LED的程序-FPGA-based VERILOG one second light an LED program
nexta
- verilog基于XILINX SPARTAN 3ESTARTER的VGA显示功能-verilog based XILINX SPARTAN 3ESTARTER the VGA display
crc-gen
- CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C and is cross-platform compatible
design_2
- 抢答定时器输入端为抢中信号，时钟信号和主持人信号。当主持人信号有效（‘0’）时，时钟信号提供计时，抢中有效之后便开始计时。先将48Mhz时钟分频为1hz的时间信号，当抢中信号有效（‘0’）来临时，将时间到信号（sjd）赋值为无效‘1’，并通过1hz时间信号输出时间显示的七段译码信号：经过一个周期，便将倒计时时间减一，并输出对应时间所示的七段译码值。经过5秒（4，3，…..，0）之后，表示时间到，将时间到信号（sjd）赋值为有效（‘0’）。-Responder timer input is gra
vhdl-2
- UART 的VHDL源代码。可在ISE, Max-Plus II,等开发环境下实现。-UART VHDL source code. The ISE, Max-Plus II, and other development environments under.
EDA-miaobiao
- EDA课程设计，作为秒计数器的系统时钟512Hz，秒表计数为两位BCD计数，具有减计数和加计数功能-EDA curriculum design, as the seconds counter system clock 512Hz, stopwatch count as two BCD counting, counting and processing has reduced counting function
VHDL_Examples_foreducation
- 一些Verylog HDL的小程序，自己琢磨一下啊-VERYLOG HDL
VHDL_Examples_for_education
- VHDL代码编程,集合了众多优秀的实例,胜过任何一本书的例子,作为教学或程序开发中调用非常合适!-VHDL code programming, a combination of a large number of outstanding examples are better than any one book's examples, as a teaching program or call very appropriate!
add_eight
- 用VHDL写的一个8位全加器的实验程序,供新手参考-Use VHDL to write an 8-bit full adder of the experimental procedures
pong
- pong in vhdl code fo fpga
CICzhengli
- 整合本站所有CIC滤波器能用的下载，并给出最好的选择，节省您的时间，花一次费用享受多次代码下载-Integration site CIC filter can download and gives the best choice, saving you the time to spend a one-time cost to enjoy several Codes