资源列表
cpld8qiangdaqi
- 基于cpld的八位抢答器，能实现按键后数显，并且按下一个键之后会自动锁住其他按键-Based on the eight cpld Responder, can achieve significant after a few keys, and press a key after the other keys are automatically locked
61EDA_D1116
- A PLD Based Delta-Sigma DAC Delta-Sigma modulation is the simple, yet powerful, technique responsible for the extraordinary performance and low cost of today s audio CD players. The simplest Delta-Sigma DAC consists of a Delta-Sigma modulat
mod_me
- 自己编写的27位宽的，求余模块，成功编译，可以下载到板子上运行-27bit mod block designed by myself ,you can systhesize the file then download the bit file to start board .
picoblaze
- 此为VHDL实现的路口红绿灯控制例子，简单实用。-This is the VHDL to achieve traffic light controlled junctions example, simple and practical.
controler
- 交通灯的控制器设计，控制红，绿，蓝，三种颜色，亮，灭，分别由三个定时器控制。- The traffic light controller design, control the red, green, blue, three kinds of color, light, destroy, respectively by three timer control.
rs232
- FPGA 数字滤波算法 资料，自己可以设计等LMS 算法-FPGA Digital Filter Algorithm for information, they can design LMS algorithm
i2c
- Some new vhdl i2c implementation. Fully tested and worked. Maybe usefull for HDL coders and FPGA designers.
Relogio
- An a perfect example of a C program for a Clock
verilog_hdl
- 多个verilog语言的例子，适合初学verilog者
NIOSII_VGA_Controller
- Nios II VGA Controller with DMA The Nios II VGA Controller with DMA is an SOPC Builder component which can be added to any SOPC Builder system to provide VGA display capability. The controller is capable of displaying the following resolutions
state
- verilog HDL下有限状态机（FSM），麻雀虽小，但五脏俱全！值得一看-under the verilog HDL Finite State Machine (FSM), the sparrow may be small, but is a fully-equipped! Worth a visit! !
eclock.VHDL
- 电子时钟，程序清晰有条理，有详细的功能仿真说明，可以一看。