资源列表
2个7段数码管
- 利用UP 实验板，设计一个8bit计数器，用其输出驱动EPF10K70RC240-4 外接的两个7段数码管
ADC_DAC_FMF_converters_vhdl.tar
- This library contains VHDL 1076 models of analog to digital and digital to analog converters. They use the VITAL packages but are not VITAL compliant.
xinhao
- 简易信号发生器，可输出三种波形，递增锯齿波发生器模块，正弦波发生器模块，方波发生器模块，波形选择器模块，vhdl-Simple signal generator can output three waveforms, incremental sawtooth generator module, the sine wave generator module, a square wave generator module, waveform selector module, vhdl
exer4
- 设计可以对两个运动员赛跑计时的秒表，verilog的大作业 -Design of the two athletes running the stopwatch timing, verilog great job
FPGAreleaseDDS
- FPGA实现 DDS_讲的非常详细,师兄的一片论文
ccd
- FPGA用于驱动线阵CCD的程序，对应东芝公司的线阵CCD，只需少量修改既可用于其他2相线阵CCD- FPGA program for driving linear CCD, the corresponding Toshiba linear CCD, with only minor modifications can be used for other two-phase linear CCD
Moving_average_algorithm
- Document detailing the moving average algorithm.
FIFO
- verilog 实现FIFO存储功能，八位数据宽度，16数据深度。-verilog achieve FIFO memory functions, eight-bit data width, the depth of 16 data.
yuvbt1120
- 采集不同分辨率视频，输出相同视频，实现bt1120编码，iic与arm通信-Different resolution video capture and output the same video coding to achieve bt1120, iic communicate with arm
si243
- Chaos indicator for Lyapunov index calculation, Is a two hidden layer back propagation neural network, Multi-machine power system simulation and flow calculation.
Lab11
- 32bits FIFO with synchronizer. pass the synthesis using Synopsys tools-bits FIFO with synchronizer. Pass the sy nthesis using Synopsys tools
MedianFilter33
- 基于3x3窗口的FPGA 调试好使的中值滤波程序,-Debugging that median filtering program