资源列表
ADDER
- simple 16-bit CSA Adder
assg-5-(serial-bit-adder)
- 4 bit adder using four full adder’s structural modeling style
xapp858
- xilinx公司的ＤＤＲ实现源码，希望对你的开发有所帮助
itc99-poli2-vhd.tar
- VHDL source code of the ITC -VHDL source code of the ITC 99
filter
- 设计一个16阶的低通FIR滤波器，对模拟信号的采样频率Fs为48KHz，要求信号的截止频率Fc=10.8kHz，输入序列位宽为9位（最高位为符号位）。-The FIR number filter example, designs a 16 ranks of low the FIR filter is a 48 khzs to the sample frequency Fs that imitates signal and request the closing of signal the fre
16-1MUX
- 16 down to 1 Multiplexer in Vhdl
jiaotongdeng
- 交通灯，模拟显示十字路口两个方向的交通通行情况。两个方向均用红、黄、绿灯指示实际状态。用LED同时显示两个方向状态的时间。时间计数方式为倒计数方式。技术参数为绿(红)50秒、黄(红)5秒、红(绿)30秒和红(黄)5秒。-Traffic lights, crossroads analog display case crossings in both directions. In both directions with red, yellow and green indicate the actu
myfifo_wave1
- fifo(1-6:1):using ip-code and rd wd interface-fifo:using ip-code and rd wd interface
VHDL_1602-LCD
- 使用VHDL语言，以纯逻辑的方式驱动1602LCD显示屏显示指定字符.通过quartusII软件进行开发。 -VHDL for 1602 LCD display.
Add2bits
- add 2 bits and display result on 7 segment (vhdl)
computer12
- 基于FPGA的八位RISC CPU的设计-FPGA-based RISC CPU design eight ....
High-Level-Design-with-SystemC
- 电子系统设计使用system C进行高层次综合high level synthesis 讲解文档,包括基本概念和流程,方法等-high-level synthesis with system C language,this document intoduce concetps,methods and flow