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  1. EDA1

    0下载:
  2. 完成一位二进制全减器的设计,采用文本输入法分别实现,分层设计,底层采用半加器和逻辑门实现。-Completion of a binary full subtracter design, implementation, respectively, using the text input method, hierarchical design, are based on half adder and logic gates.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:
    • 文件大小:381.71kb
    • 提供者:周旋
  1. HDB3

    0下载:
  2. HDB3编解码过程,本代码用vhdl语言书写,重现了HDB3编解码的详细过程。相信对广大写硬件语言的朋友有好处-HDB3 code and decode
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-03
    • 文件大小:1.09kb
    • 提供者:yuandingbo
  1. four_bit_addersubtractor

    0下载:
  2. Verilog code for 4 bit Adder/Subtructor
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-06
    • 文件大小:1001byte
    • 提供者:qt
  1. Oscilloscope

    0下载:
  2. The design is designed partly in VHDL, partly in schematic drawings and targets a Xilinx Spartan-2E FPGA. However, since the design was tailored specifically for the aforementioned boards it is highly unlikely that it can be ported to other hardware.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-09
    • 文件大小:1.77mb
    • 提供者:sami
  1. fir

    0下载:
  2. FPGA实现的FIR滤波器,很好的参考资料!-FPGA implementation of FIR filters, a very good reference!
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-31
    • 文件大小:383.07kb
    • 提供者:吴锦干
  1. attachments_05_10_2010

    0下载:
  2. VHDL program for basic gates
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-09
    • 文件大小:39.94kb
    • 提供者:sudhakar
  1. cache

    0下载:
  2. 本文给出了一个cache的所有源代码,存为txt格式的压缩包-this is a code of a cache
  3. 所属分类:VHDL编程

    • 发布日期:2013-10-19
    • 文件大小:1.06kb
    • 提供者:张的的
  1. dvbt_core_latest.tar

    0下载:
  2. The present document describes a baseline transmission system for digital terrestrial TeleVision (TV) broadcasting. It specifies the channel coding/modulation system intended for digital multi-programme LDTV/SDTV/EDTV/HDTV terrestrial services.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-27
    • 文件大小:9.42mb
    • 提供者:shen
  1. z80control_latest.tar

    0下载:
  2. z80控制器,内部包含VHDL源代码,FOF文件,基于USB借口的设计实例等.-z80 controller contains the VHDL source code inside, FOF files, USB-based design example of such an excuse.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-12
    • 文件大小:2.51mb
    • 提供者:shen
  1. bluetooth_latest.tar

    0下载:
  2. bluetooth_latest,The aim of this project is to build the bluetooth base band layer. The whole bluetooth hardware and firmware (HCI, controller and LMP) will be implemented in separate project.-bluetooth_latest, The aim of this project is to build the
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-08
    • 文件大小:1.76mb
    • 提供者:shen
  1. robot_control_library_latest.tar

    0下载:
  2. robot_control_library,包含documentation,drivers,opb_pid,opb_ps2,stepper_ctrl,等.-robot_control_library, including documentation, drivers, opb_pid, opb_ps2, stepper_ctrl, and so on.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-08
    • 文件大小:243.61kb
    • 提供者:shen
  1. ldpc_decoder_802_3an_latest.tar

    0下载:
  2. ldpc decoder 802-3an,最新版本,verilog版本.完成基于LDPC解码 -ldpc decoder 802-3an, the latest version, verilog version. LDPC decoder based on the completion
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-07
    • 文件大小:864.3kb
    • 提供者:shen
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