资源列表
cf_interleaver_6_16
- 6*16交织器的实现，非常有用，希望对你有所帮助-6*16interleaver
dct
- all ok...4 Dec 2009 ... In this method the 2-Dimensional DCT is obtained by taking two ... column-wise 1D DCT is ascertained which gives the 2D DCT of the data. ... The design is done in Verilog HDL and the simulation is done in Modelsim 6.3b.
sim_uart
- uart 收发器 verilog 代码，实现自收发功能 sys clk = 25m, baud 9600 停止位1， 无校验位； 代码实现了串口自收发功能，及把从 PC 收到的内容都发送会 PC, 其他波特率，自行修改代码即可，在 alter 的FPGA 上调试通过； -verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no par
Storm
- Storm可以同时对蛋白序列进行BLASTFASTAPfamProtParam分析软件并将结果输出到数据库中.zip-Storm can be BLASTFASTAPfamProtParam of protein sequence analysis software and the results output to the database. Zip
MYPROJECT
- 芯片与FPGA的接口代码,实现以太网10兆的接口方案之源代码-CP2200 & FPGA
wo
- sparten 3e开发板的旋转旋钮控制led灯的程序，verilog实现-sparten 3e development board led lamp rotary knob control procedures, verilog implementation
keyboard
- sparten 3E 开发板中按键盘，led灯变化的程序，verilog语言-sparten 3E development board in the keyboard, led lights change procedures, verilog language
VGA
- 用verilog在quartus环境下开发VGA彩色信号显示-verilog，quartus，vga
wode
- sparten 3e 开发板的ＶＧＡ代码实现，ｖｅｒｉｌｏｇ语言-sparten 3e development board VGA code, verilog language
jcq
- 哈尔滨工业大学计算机设计与实践实验 实验1 寄存器设计-Harbin Institute of Technology Design and Practice of Computer Experiment Design Experiment 1 register
TMS320VC5402_CPLD
- 明伟 5402 DSP 开发板的CPLD源代码-Mingwei 5402 DSP development board CPLD source code
div5
- 占空比为50 的5分频，描述语言为verilog，可以减少大家的时间!-the div5 which duty_cycle is 50, descr iption language is verilog, can reduce your time!