资源列表
based_on_FPGA_for_Portable_Vibration_Spectrum_Anal
- 这是一篇关于FPGA硬件设计的论文，主要讨论的是基于FPGA的便携式振动频谱分析仪的设计，个人感觉很有价值-This is a paper on the FPGA hardware design, the main discussion is based on FPGA for Portable Vibration Spectrum Analyzer, personal feeling of great value
vhdl
- 当接收到一个信号(D_start)时，开始计时，再收到另一个信号(D_stop)时，计时结束，得到计时时间A，然后将时间A与给定时间B进行比较，如果小于时间B,程序结束，进行下一环节(LED)，否则返回重新等待计时(cnt:=0)-When receiving a signal (D_start), the start time, and then received another signal (D_stop), the time the end of time by time A, then
syn_clk
- 一种跨时钟域的时钟同步方法，包含源文件和测试文件~-A cross-clock domain clock synchronization methods, including the source files and test files ~
Lab17sinusoidalsignalgenerator
- Lab17 正弦信号发生器设计 Lab17 正弦信号发生器设计-Lab17 sinusoidal signal generator
Lab19Tetris
- Lab19 俄罗斯方块Lab19 Tetris-Lab19 Lab19 Tetris Tetris
6ChannelAutoReverseSequential
- HEX source code for LED display
FPGAADC(VHDL)
- 用FPGA实现的ADC采样器(用VHDL编写)-ADC with FPGA-sampler (using VHDL written)
CycloneIIIEP3C25.RAR
- CycloneIIIEP3C25开发板原理图 资料-CycloneIIIEP3C25 development board schematic information
Nios2_SCH
- Nios2_SCH 原理图，可以参考设计-Nios2_SCH schematic, you can reference design
1536PointFFTfor3GPP
- 用FPGA时间FFT的方法和代码，比较实用哦-Time FFT with FPGA approach and code
BasysDemo_ISEproject
- 使用ISE继承开发环境，vhdl语言编写的Basys开发板测试程序-Basys test
ASK2T
- VHDL对基带信号进行调制，可添加包头数据。-VHDL on the base-band signal modulation, you can add header data.