- ISD asm file is 8051 microcontrole
- C_graphics_program_ImageViewerOld_code C# GDI+图形程序ImageViewerOld代码C # GDI + graphics program ImageViewerOld code
- jianpan 设计出4*4矩阵键盘对某一按键按下就在数码管显示一个数字
- EE 输入月份显示季节
- LayoutRenderer hierarchyviewer.scene.ViewHierarchyScene .
- if_infiniband Data passed in the @closure field for a request will be returned in the corresponding event. It is big enough to hold a pointer on all platforms. The ioctl used to set @closure depends on the @type of event.
资源列表
FIRdigital
- 硕士论文 FIR数字滤波器的FPGA实现技术研究-FIR digital filters the FPGA realizing technology research
vga_display
- 这里有很多vhdl的设计实例 希望可以给大家一个好的借鉴和学习资料-useful
tolltax
- toll tax coding in microcontroller
VerilogHDLxiayuwen
- Verilog HDL数字设计与综合 夏宇闻译（第二版）-Digital design and synthesis of Verilog HDL translation of Xia Yu Wen (Second Edition)
Verilogpractice
- 众多verilog常用程序例子，可以直接移植使用-Many commonly used procedures verilog example, can be directly transplanted to use
nuevolcd
- LCD 2x16 Spartan 3E, Controlador based in FSM
de0_Demonstrations
- DE0开发板上的资料,主要是他的例子,含有各种接口程序-DE0 development board information, mainly his example, contain a variety of interface program
sdram
- how to use sdram ip ， just for fpga
091655
- 基于fpga的coms摄像头 扫描，参考文献，-Fpga based on the coms camera scan, reference literature,
toolkit
- Project Control Book
alteraipcore
- Altera公司的15个ip核的源代码，找了很久才找到的一些常用ip core-Altera 15 nuclear source ip
tut_signaltapII_verilogDE2
- Altera公司原版设计手册，关于signaltap ii。-This tutorial explains how to use the SignalTap II feature within Altera’s Quartus R II software. The Signal- Tap II Embedded Logic Analyzer is a system-level debugging tool that captures and displays signals in