资源列表
dcs
- vhdl source code is very good
Verilog2001_Standard
- Using the New Verilog_2001 Standard Verifying Hardware-Using the New Verilog_2001 Standard Verifying Hardware
UART_EX
- Uart 232 module example divied by 3 module.
pli_handbook_examples_pc
- The Verilog PLI Handbook(contained code)
DCT
- DCT / VHDL Discrete Cosine Transform
FFT
- 用VHDL语言建立了quartus工程，可进行dsp处理-VHDL dsp
equlizervhdl
- 实现数字均衡器的设计,是我们最近正在做的项目,希望对大家有用-Digital equalizer design is our most recent projects are doing, we want to be useful
TimeQuest
- Timequest的应用试验，包含Timequest的例子。-Timequest application testing, including Timequest example.
32bitcarrylookaheadadder
- 32位超前进位加法器的源代码和testbench-32 bit carry look ahead adder and its testbench
QuartusIITimequest
- 关于quartus中的Timequest Timing analyzer的讲解PPT，由Altera提供-About quartus in Timequest Timing analyzer' s explanation PPT, provided by the Altera
ref-sqroot
- 求平方根的ip核，Altera提供，可以用在FPGA上，是AHDL语言写的，不开放源码-Square root of the ip seeking nuclear, Altera provides, can be used in FPGA, is written in AHDL, not open source
FPGA
- FPGA入门教程包含数字电路基础FPGA简介FPGA开发流程RTL设计QuartusII设计实例和仿真-FPGA Tutorial Introduction contains digital circuits based on FPGA FPGA RTL design development process, design example and simulation QuartusII