资源列表
manch
- 该文件是一个完整的工程文件，用VerilogHDL语言编写，包括曼彻斯特编码器的设计文件和仿真测试文件以及解码器的设计文件和仿真测试文件。在Modelsim中仿真测试通过。-The document is a complete project file, with VerilogHDL languages, including the Manchester encoder design documents and simulation test files and decoder design
sumador
- sumer vhdl code for FPGA of Xilinx
GAFF
- 伽罗华域GF（q）乘法器设计,完整的源代码。-Galois field GF (q) multiplier design, the complete source code.
jiyuchuankoujishu
- 计算机在HDL语言下实现串口技术,UART相关资料-BASIC IN HDL language,chuankou jishu
bluespec-80211atransmitter_latest.tar
- This package implements a parameterized baseband hardware logic for an 802.11a Transmitter. This project has since been subsumed by the OFDM baseband project which can also be found on opencores.-This package implements a parameterized baseband har
hdbn_latest.tar
- This “core” is actually two cores – an HDB3/HDB2/B3ZS Encoder that converts NRZ data into P and N pulses according to ITU-T G.703, and a HDB3/HDB2/B3ZS Decoder that converts P and N pulses into NRZ data according to ITU-T G.703.
ourdev_457422
- Verilog HDL教程包含大量实验例子-Verilog HDL tutorials contain a large number of experimental examples
d1_dec
- d1(BT.656) video decoder VHDL code
FPGA
- 里面有用NIOS2与SOPC的做的一个串口程序，还有详细文档步骤，对于学习SOPC者有很大帮助-Inside useful NIOS2 to do with the SOPC a serial program, as well as detailed documentation steps, for the study were of great help to SOPC
finallab
- introduction to veri well and behaviural modeling code for 4 to 1 mux
FINALAB
- it is veri log code for ALU comparator and shift register using veriwe-it is veri log code for ALU comparator and shift register using veriwell
encoder_binary
- 一个简单的FPGA实现的编码器，但程序中有详细的说明，并附有测试凳，可以以此为基础设计更复杂的编码器-FPGA realization of a simple encoder, but the procedure described in detail, together with a test bench, you can as a basis for designing more complex encoder