- a 利用LABWINDOWS/CVI写的二值图像形态学处理
- des2 des加密算法c++版本
- GOST 前苏联的加密标准的代码实现.
- TIZIP some importante files for dsp F2812
- Async-Notification-Sample The Async Notification sample demonstrates how to implement AsyncNotification to communicate between registered applications and printing components that are loaded in the spooler.
- syrajght 扩展后的中点法画直线程序
资源列表
clock
- 这个程序是用verilog hdl语言编写，实现在数码管上显示时间，暂不支持调整-This program is written in verilog hdl to achieve in the digital tube display time, withhold support to the adjustment
seg
- 数码管显示（verilog） 自己写的 在数码管上显示01234567 动态显示-Digital LED display (verilog) himself wrote in the digital tube display 01234567 dynamic display
lcd
- FPGA控制lcd1602(verilog)-FPGA control lcd1602 (verilog)
E1SyncPkg
- The package constructor for E1sync example.
baudTest_TB
- baud testbenchfor sync and assync serial communication
AciAudioClks_TB
- Audio Codecs Clks synth for tlv
FreqSynth
- Frequency synth example with primitives. Very simple.
E1Tsi_TB
- TSI testbench for E1
ic_design_flow_vhdl
- vhdl code and icdesign flow for mentor graphics ic design tools
Design_of-8_Bit_Microcontroller
- vhdl code and tutorial for 8 bit microcontroler
viterbi
- verilog code for viterbi encoder and decoder
attachments_2010_01_29
- dct and idct vhdl code