资源列表
Verilog秒表设计
- 用verilog在basys2开发板上实现一个具有置零、开始、暂停、记忆功能的秒表。(Implement a stopwatch which containing reset,pause,start,memory functions with the verilog on the vivado based on the basys2 development board.)
uart
- uart的Verilog代码，经过测试没有问题，有测试文件-uart Verilog code, no problem tested, the test file
ppt
- 介绍 AXI 协议的PPT, 和一个 slave（verilog实现） 接口的简单实现，需要的可以看看；-AXI protocol described PPT, and a slave interface is simple to achieve, need to look at
LCD1602
- 可以实现在LCD1602液晶显示屏第一行左侧第一位的位置循环显示0~9，并且可以用一个拨码开关BM8实现显示的复位功能。-LCD1602 LCD display can be achieved in the first position of the loop on the left side of the first line of the display from 0 to 9, and can be used to achieve a DIP switch BM8 display rese
S_FIFO
- 自己编写的同步Verilog FiFO 还是不错的 可以-Verilog 同步 FIFO
DS18B20
- VHDL实现DS18B20测温，实现平台XC3S500E-VHDL DS18B20 temperature platform XC3S500E
dds1
- 本历程使用FPGA根据DDS原理使用VHDL语言编译成功的产生一些固定频率的DDS-The process of using the FPGA using the VHDL language according to the principle DDS compile successfully produce some fixed frequency of the DDS
ieep1.6
- low-power 16-bit CMOS D/A converter for portable digital audio is described. The converter is based on current division. To guarantee monotonicity and a good small-signal reproduction, a dynamic segmentation technique is used. A geometric avera
verilogFIR
- 本源码为Verilog的FIR数字滤波器 测试后性能很不错的-The source of the FIR digital filter for the Verilog test performance is very good
verilogFIR
- 基于verilog的FIR滤波器程序设计（调试过的）-verilog
EP1C8Q240C8N_PCB
- 本文档为FPGA的最小系统板，型号为EP1C8Q240C8N，包含两片FLASH,没有SDRAM. 有这方面需要的同学，欢迎下载-This document is the minimum system board based on FPGA EP1C8Q240C8N, including two pieces of FLASH, no SDRAM. Welcome to download for the students who need!
sanjiao
- 用FPGA产生正弦波信号，没有用到D/A转换器，采用的是pwm原理，占空比可调技术。-Using FPGA to generate sine wave signals, did not use the D/A converter, using the pwm principle, variable duty cycle technology.