资源列表
modelsim-se-10.1a-crack
- modelsim10.1a的破解文件，已测好用，破解简单-modelsim10.1a crack file, have been measured easy to use, simple crack
uartfifo
- verilog实现的fifo到串口数据通信-verilog achieve fifo to the serial data communication
hispi_example_design
- hispi high spededddddddddddddddd
Adder_4bit
- Verilog Program for a 4bit Adder
ex4
- 串口通讯 可选波特率 verilog 源代码-Selectable baud serial communication verilog source code
aircity
- 通过FPGA开发板上的蜂鸣器实现对乐曲天空之城的演奏，编码比较简单，主要是提供一种思路-Through the FPGA development board buzzer realize music playing Laputa, coding is relatively simple, the main idea is to provide a
03.Anvyl_KYPD_SEG_Demo
- 用VHDL写的KEY程序，使用与xilinx开发板。-KEY program written using VHDL, use and xilinx development board.
text9
- 数字电路实验：计数器。使用小规模集成器件设计计数器的；使用中规模集成器件设计计数器的；Verilog HDL对计数器的建模-Digital circuit experiment: Counter. The use of small-scale integrated device design counter Use medium-scale integrated devices designed to counter Verilog HDL modeling counter
lab05
- edk xilinx官方提供的学习资料 非常适合初学者 进步很快-edk xilinx
1616dianzhen_move
- 16*16点阵，动态显示“欢”字，串行输入-16* 16 dot matrix, dynamic display " love" word
t1_comm
- 该程序包括数据的发送，加密，奇偶校验，接收，解密等模块，实现了一个完整的收发操作。为了测试方便，我们将接收到的数据直接引入发送端口，为此，我们编写了测试脚本文件，验证程序的正确性。该程序模块较多，读者可参考压缩包内的原理框图文件，以便于理解。-The program includes sending, encryption, parity, receive, decrypt data modules to achieve a complete transceiver operation. In
esign
- FPGA的机载音频管理系统通信测试卡设计-FPGA on-board audio card management system Communications Test Design