资源列表
CoreSPI_21_eval
- SPI IP核源码，包括Verilog和VHDL两种语言源码-SPI IP core source code, including the two languages Verilog and VHDL source code
spiflashcontroller
- -- This program is free software you can redistribute it and/or -- modify it under the terms of the GNU General Public License -- as published by the Free Software Foundation either version 2 -- of the License, or (at your option) any later ver
8255_OSED
- 8255a的完全功能，可作为8255a的ip核-function of 8255a
comparator
- 使用verilog语言，在FPGA开发工具ISE上实现比较器功能。-The use of Verilog language, in FPGA ISE development tools to achieve the comparator function.
FPGA-VHDL-Time-Constraints-example
- FPGA VHDL Time Constraints Example
fpga_tcl
- Altera FPGA的特殊管脚的连接(中文).doc TCL_教程.pdf-Altera FPGA tcl
基于vhdl的出租车计价器
- 利用VHDL语言设计了一种出租车计费器,能够实现计费及显示的功能.采用动态扫描技术分别显示汽车载客时行驶里程、中途停车等待时间及总费用.在Altera公司的QuartusⅡ9.0开发环境下进行了源程序的编译、仿真,下载到FPGA芯片EP 1K30TC 144-3进行了硬件测试,具有一定的实用价值.
1024_FFT
- 1024点FFT快速傅立叶变换，包含说明文档和VHDL源代码，16位输入/输出，带DMA功能，xilinx的ip-1024-point FFT fast Fourier transform, and includes documentation, VHDL source code, 16 input / output, with DMA function, the ip xilinx
shfrtled
- 使用状态机思想实现VHDL LED跑马灯功能-Thinking of using the state machine VHDL LED Marquee function
ADS8323
- 本设计是基于EP4CE15F17C8N和ADS8323的16位ADC数据采集和12864显示的程序-The design is based on a program EP4CE15F17C8N and ADS8323 16-bit ADC data acquisition and display of 12864
数码管显示
- 在FPGA EGO1的口袋平台上实现数码管滚动显示学号的功能(Rolling on the digital tube to display the school number)
DDS_generation
- 基于Altera FPGA的DDS 模块 - DDS generation module based on Altera FPGA