资源列表
ele_clock
- 时钟（时分秒LED显示） 秒表（计时） 闹钟（自动报时）-alarm clock
Ward-Calling-System_-timing-_latch
- 病房呼叫系统 锁存器 计时模块 优选模块 时间模块-Ward calling system timing module latch time module selection module
DCT_vhdl
- IDCT-M is a medium speed 1D IDCT core -- it can accept a continous stream of 12-bit input words at a rate of -- 1 bit/ck cycle, operating at 50MHz speed, it can process MP@ML MPEG video -- the core is 100％ synthesizable-IDCT-M is a medium speed
QPSKdemodulation
- QPSK解调，以及对相位模糊的解调。VHDL代码，测试通过-QPSK demodulation and phase ambiguity
COD_MANCHESTER
- Manchester Coding vhdl code
matlab_quartus_ii_MIF
- matlab quartus ii MIF
309361_88321a222b5ae22c
- DCT 图像处理 基于VHDL语言 简单可行-DCT image processing language based on VHDL
Killswitch
- 这是用来KILLSWITCH的开关， 是采用汇编语言的编写。-This is used to to KILLSWITCH the switch, and is written in assembly language.
pwm_source
- Altera官网上关于SOPC中自定义组件（PWM）的实例，官网上现在没了。。可很多书上都在用-Altera in the official line on the SOPC custom component (PWM) of the examples are not the official line. . Can be a lot of books are in use. . .
dividers
- verilog格式的除法器，试过了，很好用，再也不要为触发器发愁了-Verilog format divider, tried, very good, and no longer for the flip-flop not to worry about the
crc_verilog_xilinx
- CRC,对于研究通信的有重要意义.利用VERILOG实现8位，16位等CRC原理,-CRC, the study of communication are important. VERILOG to achieve the use of 8, 16, such as CRC principle,
DA(AD768)
- AD768产生锯齿波的源码，DA转化的最基本操作。-AD768 sawtooth source code, the basic operation of DA conversion.