资源列表
asymmetric_fifo
- 高速同步非对称FIFO,verilog 代码，很有价值的参考设计。-Asymmetric high-speed synchronous FIFO, verilog code, and very valuable reference design.
RAM
- this is a souce code for synchronous RAM
1DCT_VHDL
- VHDL Behavioral Model for 1D DCT operation Algorithm : Calculates the 1D DCT coefficients. DCT Points range from 8 to 32. There is double buffering at the input, to allow continuous usage of DCT engine.-VHDL Behavioral Model for 1D DCT operation
timing_ctrl
- 接收时序控制器的verilog描述，及仿真波形。-Receive timing controller verilog descr iptions, and simulation waveforms.
DigitalclockinVHDL
- it is the program for VHDL digital clock
vhdlcode3
- here is gangadhar call by mailing me
verilog_study
- it about using veriolog complement some project,thanks!
vhdl_sdram
- Altera Sdram vhdl 控制代码-Altera Sdram vhdl control code
source
- SDRAM控制器源代码，是ALTERA公司的IP源核，很好很强大-SDRAM controller source code, very very strong
nios2crc
- 基于niosii和sopcbuilder的冗余校验-Based on niosii and sopcbuilder redundancy check
State-Machine
- This gives the function of state machine
library-ieee
- 用VHDL语言编写的锯齿波，并且包括锁存器的生成代码-With the VHDL language sawtooth, and latch generate code