资源列表
vga_gen
- VGA Control with VHDL in Altera DE0 Board
dianzizhong
- 使用Verilog语言编写的电子钟，课堂小实验，经过测试可用。-Electronic clock, with Verilog language classroom experiments, after testing is available.
Design_74LS138
- 利用Active-VHDL 来仿真测试74LS138 译码器，74LS138 译码器是3 线-8 线译 码器。-To the use of Active-VHDL simulation test 74LS138 decoder, 74LS138 decoder is a 3-wire-8 line decoder.
divider_60
- 用Verilog语言实现了数字钟的功能，支持平台是alter公司的cyloneII。-Verilog language with a digital clock, support platform is alter the company cyloneII.
ADcollector
- AD电压采集是基本功，这个是C8051F410的电压采集模块，自已学习时开发的。-AD voltage acquisition is the basic skills, this is C8051F410 voltage acquisition module, from the development of learning.
example10 can 243 -2
- DSP 程序的测试 很有用的 仪器上面用的-DSP testing procedures very useful in the above apparatus
uart(Verilog)
- uart 测试源码，已经测试过，非常好用-uart test code
dss_201403
- 使用verilog编写的，测试用多路串口通信信号源，用于fpga产生多路测试用串口信号，配置外围电平转换电路可以设计一个多路可编程数字信号源-Use verilog written, multiple serial communication test signal source for generating multiple test fpga serial signal, configure the external level shifting circuitry can design a
kcpsm3
- kcpsm3.v picoblaze Xilinx-kcpsm3.v
LCD
- 液晶控制器，verilog程序，仅供参考，上网找了好久没找到。-LCD controller, verilog program.
自定义逻辑PWM的例子
- 是一个用vhdl语言编写的pwm程序，可以方便地用来和nios连接，实现对nios的功能扩展。-is a VHDL language with the PWM procedures can be used to facilitate connections and nios, nios to achieve a functional extension.
crc_verilog_xilinx
- CRC校验码，用于对数据流进行crc校验。 主要有CRC_16,CRC_8,CRC_32校验。 所用语言为Verilog HDL.-CRC code for the data flow crc check. Main CRC_16, CRC_8, CRC_32 check. The language used for Verilog HDL.