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四位移位寄存器用vhdl语言设计
- 四位移位寄存器用vhdl语言设计
54088960verilog_multicrc
- CRC校验码生成器的程序编码，verilog编写-The CRC generator to the program code, verilog write
65905857-A-A
- vhdl code for risc processor-vhdl code for risc processor...........................
viterbi
- (2,1,9)卷积编解码器，译码部分采用Vitebi译码算法，设计使用Verilog HDL语言，在Modelsim平台下仿真通过
VGA_monitor_interface
- This code its referent to VGA monitor interface
Digital-signal-
- 基于VHDL数字信号发送和接收，是VHDL初学者值得参考的程序代码-Based on VHDL digital signal sent and received，Is VHDL is worth reference beginners program code
dcm
- 本人正在学习vhdl语言，买了套开发板，这些是配套光盘里的内容，非常难得，网上找不到的-I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !
luan-van
- design calculator using verilog
uart_VHDL
- UART的一段VHDL程序，可以作为参考
key_music
- 简易硬件电子琴 在开发板上实现一个简易电子琴，按下KEY1~KEY7 分别表示中音的DO、 RE、MI、FA、SOL、LA、SI 按住KEY8 再按KEY1~KEY7 分别表示高音的 DO、RE、MI、FA、SOL、LA、SI。通过这个实验，掌握利用蜂鸣器和按键 设计硬件电子琴的方法。-Simple hardware keyboard In the development of board achieve a simple keyboard, press KEY1 ~ KEY
uart protocol transmission
- todays data trans mission consist of more secured and low power with redused cost in technique well for that here is universel asyncronous reciever and transmitter with some protocol which make it to be secured
source
- A major obstacle that stands in the way of efficient test response compaction are the unknown values (x-values) captured by scan cells during testing. If test responses with x-values are compacted, some of the outputs of the compactor may als