资源列表
div_clk
- verilog实现任意时钟分频，简单明了，打开modelsim-change directroy-do sim .do 即可-Achieve any clock divider, simple, open modelsim-change directroy-do sim. Do to
fsm_seq_det
- verilog 状态机实现序列检测。简单明了，打开modelsim-change directory -do sim.do 即可-State machine sequence detection.
clk
- 五分频时钟的产生,分为两个，一个是不带边缘检测，另外一个带边缘检测-Fifth generation of the clock frequency is divided into two, one is a non-edge detection, and the other with edge detection
DE2_Top
- 此设计是一个裸机的设计，其中包含在DE2开发板所有的引脚分配。它还包含一个与所有的对应于每个引脚的输入/输出端口的Verilog模块。这可以被用来作为一个起点上的电路板的设计。-This design is a bare-bones design containing all the pin assignments available on the DE2 board. It also contains a Verilog module with all the input/output por
Rs232Memory
- 使用ram 进行rs232 通信 非常实用-Using ram for rs232 communication
16bit_ram
- 利用vhdl语言在fpga实现十六位的ram 使用非常方便-Using vhdl fpga implementation sixteen languages in the ram is very convenient to use
ramipcore
- 使用vhdl 语言在fpga环境下实现ram ip core-Environment in fpga vhdl language used to achieve ram ip core
DE2_115_IR
- Verilog IR Receiver decodes and process signal through FPGA and display on the 7-segment displays in hrxadecimal format.
DE2_115_i2sound
- Simple FPGA karaoke machine, that usi Microphone-in, line-in and line-out on DE2-115 board to mix two audio streams realtime
DE2_115_SD_Card_Audio_Player
- FPGA project demonstrate how to play music stored on SD card via WM8731 Audio Codec
DE2_115_Synthesizer
- FPGA implementation of simple Multi-tone Electronic Keyboard using DE2-115 board with a PS/2 keyboard and speaker
jiaotongdeng
- FPGA 交通灯控制器 基于fpga 已经仿真验证请放心下载-FPGA traffic light controller