资源列表
PLL
- 基于FPGA的锁相环应用，原理图输入法，较为直观，锁相的效果无抖动-FPGA-based PLL applications, schematics input method, more intuitive, the effect of jitter PLL
jiaotongxinhao
- vhdl语言编写的，在QuartusII下，交通信号灯控制器-vhdl language, in QuartusII, the traffic signal controller
ledarray
- 用vhdl语言,在QuartusII下,点阵显示欢迎使用系统-Using vhdl in QuartusII, the dot matrix display welcome to use the system
codic
- 8级cordic 算法verilog-8 cordic algorithm verilog
IFFT
- 赛灵思OFDM的发射机IFFT处理，Verilog语言-OFDM Transmitter IFFT
VGA
- 基于FPGA的显示器驱动代码 能够驱动vga显示器 简洁的描述了vga时序协议 对FPGA初学者很实用-FPGA-based display driver code can drive vga vga monitor concise descr iption of the FPGA timing protocol is very useful for beginners
296517dcm
- 基于ISE 12.4的IP 核调用 DCM 其功能是将开发板上的系统时钟变为任意的所需时钟 适合初学者学习-ISE 12.4 IP core based on DCM and its function is to call the board will develop into any desired system clock clock for beginners to learn
756Rs232
- 基于FPGA的rs232 并将收到的数据写入存储器件中（片能的存储器）再将写入的数据读出并发送适合初学者学习-FPGA-based rs232 and writes the received data storage device (memory chip capacity) suitable for beginners to learn
90166ram_16bit
- 基于FPGA的片没ram的读写功能代码，能够写入和读出16bit的数据，适合初学者学习和模仿使用-FPGA-based tablets did not ram read and write function code can be written and read out the 16bit data, suitable for beginners to learn and imitate Use
33017ram(1)
- 基于FPGA的片没ram的读写功能代码，能够写入和读出16bit的数据，适合初学者学习和模仿使用-FPGA-based tablets did not ram read and write function code can be written and read out the 16bit data, suitable for beginners to learn and imitate Use
clock_generator
- 802.11a时钟产生、分频模块，verilog源码-802.11a clock generator, frequency module, verilog source
IFFT
- FPGA实现IFFT模块，verilog源码-FPGA implementation IFFT module, verilog source