资源列表
shuzipaobiao
- 数字跑表 已经验证 请放心下载 基于fpga-Digital stopwatch has been verified, please rest assured download
DE2_115_TV
- FPGA project to overlay text/graphics information on video that uses Composite videc ADC ADV7180 and VGA DAC ADV7123
zhuangtaiji
- 基于FPGA 的状态机 已经验证 请放心下载-FPGA-based state machine has been verified, please rest assured download
PS2
- ps2 接口设置 基于fpga 已经验证 请放心下载-ps2 fpga-based interface settings have been verified, please rest assured download
DE2_115_PS2_DEMO
- Simple PS/2 controller in Verilog HDL to demonstrate bidir communication between PC/2 controller and PC mouse slave device
DE2_115_WEB_SERVER_MII_ENET0
- Simple HTTP server using sockets interface of NicheStack TCP/IP and NIOS II SCPU to serve HTML, JPEG, GIF PNG, JS, CSS, SWF, content using RGMII on DE2-115 board
sine-function-generator-design
- 一个正弦发生器的设计，应用于EP2C35F672C6开发板，仿真环境为Quartus II 9.1 -A sine generator design, based on EP2C35F672C6 board. Simulated in Quartus II 9.1
3.UART_test
- FPGA的UART通信实验，已经过验证，使用verilog程序编写。-The FPGA UART communication experiment has been verified using verilog programming.
duty-cycle
- FPGA的测试占空比程序，已经过验证，自己编写，使用verilog程序-FPGA-duty test procedures have been verified, their preparation, use verilog program
Fix-data-send-UART
- Fix data UART send and receive verilog codes.
uart_tb
- simple UART testbench code.inlucding
uart_if
- ram source read mode UART CODES.