资源列表
AMI
- 本代码是用verilog写的AMI码的编码的程序，简单易懂，经调试是正确的。-This code is written in AMI code with verilog coding procedures, easy to understand, after debugging is correct.
7-segment_digital_tube_decoder_design
- VHDL中7段数码管译码器设计与实现的实验报告，包括源代码-VHDL in the 7-segment digital tube decoder design and implementation of the experimental report, including the source code
VHDL_design_of_sequence_detector
- VHDL中序列检测器的设计的实验报告，包括源代码-VHDL in the design of sequence detector test reports, including the source code
ROM_based_sine_wave_generator_VHDL_design
- VHDL基于ROM的正弦波发生器的设计的实验报告，内附源代码-ROM-based sine wave generator VHDL design of experiment reports, included the source code
VHDL_digital_lock_design
- VHDL课程的源代码数字密码锁的设计与实现的实验报告，内附源代码-VHDL source code for the course digital code lock design and implementation of the experimental report, included the source code
carryriple
- carry riple with model sim
i2c
- 模拟I2c的源程序，可以用51来控制传输数据-Analog I2c the source can be used to control the transmission of data 51
GrayCnt
- 格雷码计数器 VerilogHDL语言编写-Gray-code counter using VerilogHDL language
camera_len_con
- 一个摄像机镜头远程控制C程序，采用PELCO-D和PELCO-P自动识别协议，通信速率：1200/2400/4800/9600四种，镜头反持类型：直流和止进两种，通过P1.0选择，当前使用的CPU型号为STC12C5201系列-A camera lens remote control C program, using PELCO-D and PELCO-P automatic recognition agreement, the lens counter-holding types: DC an
RS232
- RS232_串口通信的发送端verilog源程序代码-RS232_ serial communication sender verilog source code
StaticPLL
- 介绍FPGA中数字锁相环的设计方法和应用的文档-Introduction of Digital Phase-Locked Loop FPGA design methodology and application documents
FSK_MOD_my
- verilog语言设计的用于fsk调制的源码-verilog language design for fsk modulation source