资源列表
fpga
- 为学习FPGA设计人员提供一些经验，提高FPGA使用效率，-For learning FPGA designers to provide some experience and improve the efficient use of FPGA,
SRDFF
- Zip file contains the shiftregister code using verilog HDL
verilog_hdl_code
- 适合学习verilog 的初学者，这都是一些简单例子，希望有帮助-Suitable for beginners to learn verilog, these are some simple examples, want to help
dianziqin
- 这个程序是利用Quartus II编写的利用数控分频器设计硬件电子琴，主系统由3个模块组成，顶层设计文件内部有三个功能模块：SPEAKER.VHD 和TONE.VHD和NoteTabs.vhd。模块TONE是音阶发生器，模块SPEAKER中的主要电路是一个数控分频器，NOTETABS模块用于产生节拍控制和音阶选择信号。-This program is the use of Quartus II design prepared by the use of CNC divider hardware
uart232
- 基于FPGA的异步串行通行，用MAX232转化的，利用VHDL语言写的，都已调通，有很大的使用价值！-FPGA-based asynchronous serial passage, with MAX232 conversion using VHDL language written in, have been transferred pass, there is a great value!
TOP_WHIF_CAMRA_240_320
- code in vhdl to frame_gerber form camera 320x240 pixle
PetaLinux_Bootloader_Solutions
- A bootloader is required to bring up an FPGA-based Linux system from a power-on or reset. PetaLinux offers a pre-packaged, dual-phase bootloader solution, specially developed and customised for FPGA-based embedded Linux systems.
nr_divider
- This a simple vhdl code that perform division using the non restoring algorithm which is often handy-This is a simple vhdl code that perform division using the non restoring algorithm which is often handy
modu
- this the verilog code that performs the modulus function ... most importantly it is synthesisable... uses the repeated sub algorithm-this is the verilog code that performs the modulus function ... most importantly it is synthesisable... uses the repe
clock_divider_lab
- Clock divider lab uusing xilinx tools, and simulator like modelsim
modeling_memory
- HDL source code for clocking excercise
mbtutorial
- This tutorial guides you through the process of using Xilinx Embedded Development Kit (EDK) software tools, in which this tutorial will use the Xilinx Platform Studio (XPS) tool to create a simple processor system and the process of adding a cust