资源列表
VHDLforFPGA
- vhdl language for fpga
honhludeng
- 软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 用VHDL语言仿真交通灯-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Using VHDL language simulation of traffic lights
yuelao
- 软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 用VHDL语言仿真歌曲刘德华的《月老》-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Using VHDL simulation language song Andy Lau' s " 月老"
naozhongsheji
- 软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 闹钟设计-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Alarm Clock Design
sell
- 软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 自动售饮机 电话计费器程序-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Drink vending machine telephone billing program
clock
- 软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 多功能数字钟-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Multi-function digital clock
song
- 软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 梁祝乐曲演奏电路-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Butterfly music concert circuit
erfenpin
- 二分频的实现 二分频的作用是将测相范围由0°~180°扩大到0°~360°。-Two sub-band implementation of the two is the role of sub-frequency measurement phase will range from 0 ° ~ 180 ° extended to 0 ° ~ 360 °.
FPGA_radar
- 优秀硕士论文，基于FPGA的雷达信号模拟器设计，对学FPGA的，特别是学雷达的同学有很好的参考价值-Outstanding master s thesis, based on radar signal simulator FPGA design, FPGA-on study, in particular the study of radar has a good reference Student Value
FADDER_2
- 32位全加器 在querters II 下面运行成功 仿真 验证均已成功-32-bit full adder at querters II following the success of simulation runs have been successful
vhdl_example
- 几个用VHDL语言编程实现的电子设计，有详细的原理介绍和源程序-VHDL language programming with some of the implementation of electronic design, has a detailed introduction of the principle and source
SDR_SDRAM_vhd
- SDR SDRAM的VHDL描述，比较详细，还有数据手册-SDR SDRAM the VHDL descr iption, more detailed, have data sheet