资源列表
QAM_verilog
- 基于FPGA的16QAM，用verilog编写，其中DDS为自己编写，含设计文件和testbench。已通过moldesim软件仿真。 -FPGA-based 16QAM, with verilog writing, including DDS for their preparation, including design files and testbench. Simulation software has been through moldesim.
gdi1
- Viterbi decoder is used for decoding data encoded using Convolution Forward Error Correction codes or data that suffers inter-symbol interference. They occur in a large proportion of digital transmission. Viterbi decoders employed in digital wire
SUBWAY
- ① 设计一个符合武汉市现行计价标准的地铁自动售票机。②每个地铁站设置一个开关，设置“10元”和“1元”两个投币口（用开关模拟），设置四个数码管，分别显示投币金额和找零金额，用指示灯表示出票。每次操作限购1张票。 -1、Designing a valuation in line with the current standard of Wuhan Metro ticket vending machines。2、Each subway station setting a switch, set
demo4
- AXI4-stream协议，用于调试，测试代码，IPcore-The AXI4-stream protocol, used to debug, test code, IPcore
Infrared-light-transmission-
- 将音频信号输入到电路中，发射端利用红外光发射出去，接收端进行接受，经AD处理，由声音的高低控制灯的量灭，另外将温度实时采集并显示在数码管上，详情请见压缩包中的文档-Audio signal input to the circuit, transmitter with infrared emission, the receiver to accept the AD processing, controlled by the sound of the amount of light, in addi
FFT16
- FFT变换的代码，适合初学者学习。16点FFT-FFT transform code, suitable for beginners to learn. 16 FFT
cordic
- cordic的代码，适合初学者学习和交流-cordic code, suitable for beginners to learn and exchange
CfgDDS_9910
- dds ad9910配置的verilog hdl程序，模块化设计，输入待配置的数据，字长，启动信号，即可自动产生时序，完成一次配置，模块还有done握手信号，方便用户调用时，反复多次配置。-dds ad9910 configuration verilog hdl program, modular design, the input data to be configured, word length, the start signal, the timing can be automatical
m_serial
- m序列产生。3个300阶m序列级联，产生近似随机的数数。输出包括串行输出的随机时钟和并行输出的32位的随机数。-m sequence generation. 3 300 m-order sequence cascade, resulting in an approximate number of random numbers. Output 32 of the random numbers and the parallel clock output comprises serial output
r7lite
- R7Lite是基于Xilinx的Kintex7系列FPGA的PCI Express参考设计代码，PCIe 2.0 4x模式，包括了FPGA实现，Linux下驱动和测试例程。-R7Lite is a PCIe Reference design based on Xilinx Kintex7 FPGA,including FPGA code ,Linux Driver and Testing App
MB
- 基于VHDL语言数字秒表设计,在FPGA实验平台下开发-Digital stopwatch design based on VHDL, FPGA experimental platform under development
scan_led
- 每个时钟，计数时间，实现8的扫描显示，在数码管上依次显示13579bdf，可以选择EDA实验箱，FPGA EP1C6Q240C8。-Each clock, counting time, achieve 8 scan display, turn on the digital tube display 13579BDF, can choose EDA experimental box, FPGA EP1C6Q240C8.