资源列表
run_module
- 基于verilog HDL的流水灯的源代码，可在FPGA开发板上运行。欢迎大家下载交流！-Based on the water lights verilog source code, welcome to download the exchange! ! !
ad_rx_module
- 基于verilog的串口通信接收部分代码，欢迎下载交流！-Receiving part of the code verilog based serial communication, welcome to download the exchange!
12_lcd_spi
- 用于FPGA开发板的LCD显示实验源码包，欢迎大家下载交流，有不周之处还望批评指点！-For FPGA development board LCD display experiment source package, welcome to download the exchange, there are ill also look criticism pointing!
07_number_mod
- 基于verilog的数码管显示,浅显易懂，下载即可调试使用-Verilog based digital display
NCO_test
- FPGA的压控振荡器NCO完整Verilog工程代码，测试输出1KHZ sin波。signaltap抓取没问题。-VCO NCO complete FPGA Verilog code engineering, test output 1KHZ sin wave. signaltap crawl no problem.
water_light
- Verilog语言的流水灯设计程序，对初学者很有用。-Water lights Verilog language design program useful for beginners.
async_fifo_prj
- Verilog语言写的异步fifo，包含随机数产生电路和testbentch,直接可用于实际工程中。代码为华为内部代码。相信你会喜欢。-Verilog language used to write asynchronous fifo, including random number generation circuit and testbentch, can be used directly in the actual project. Code for Huawei internal code
CLK_GEN
- Xilinx FPGA时钟倍频电路，使用内部全局时钟、DCM，可参数化。-Clock Generater for Xilinx FPGA
STDL80.ZIP
- Leonardo综合器用STDL80 0.5um综合库，安装见说明，找到它真不容易。-STDL80 0.5um ASIC Library for Leonardo
mt48lc32m16a2
- SDRAM的仿真模型Verilog。用于美光mt48lc32m16a2，可在ModelSim下用。-Simulation Model of SDRAM
triangular_vhd
- This the triangular wave generation vhdl code to check the wave form in modelsim simulator-This is the triangular wave generation vhdl code to check the wave form in modelsim simulator
yuv422tobt1120
- yuv422转bt1120时序，vivado工程，用tpg做信号源-yuv422 to bt1120