资源列表
ieep1.3
- 10-b 50-MHz digital-to-analog (D/A) converter is presented which is based on a dual-ladder resistor string. This approach allows the linearity requirements to be met without the need for selection or trimming. The D/A decoding scheme reduces th
uart_ram
- 串口接收数据校样后存入双口ram,接收完整帧数据后，置中断，通知串口发送-After receiving proof serial data stored in dual port ram, receive a complete frame of data after the interrupt, serial port to send notifications
lpf
- 利用altera的IP核构建的并行数字滤波器，实现100kHZ低通，带外抑制40dB-Altera use IP cores constructed parallel digital filters achieve 100kHZ low pass, band rejection of 40dB
FPGA 正交编码 verilog
- 用Verilog写的2倍频率正交编码的仿真测试程序，仿真波形已经调出
top
- FPGA开发UART软件有一定的参考价值，请参考该软件进行编译Altera软件编写的-FPGA development software UART has some reference value, refer to the software to compile software written Altera
license_ISE_11_to_12_AVNET-yyy
- ise11.1的license，包括了fifo等IP核，谢谢大家的光顾。-ise11.1‘s license which provided some ip like fifo.
sync_fifo
- 同步fifo实现代码，包括的参数：数据宽度、fifo深度、地址宽度；状态信息包括：full, empty。-verilog RTL code which implement a synchronous FIFO function with data width, fifo depth, address pointer width parameterized.
I2C_contrl_LED
- I2C的top文件，是按照标准的I2C协议编写的，已通过调试，放心使用-I2C s top document is written in accordance with standard I2C protocol has been through debugging, ease of use
PCF8563
- quartus ii 实时时钟pcf8563工程及源码 Verilog hdl 实现iic总线-quartusii realtime pcf8563 project and code and IIC verilog hdl
VGA
- quartus ii verilog hdl 实现VGA时序及显示的工程和源程序 -quartus ii verilog hdl vga timing project and source code
CacheFromScratchFinalWeek_ise12migration
- VHDL implementation of an 8-bit multilevel cache. Produces timing diagrams when run on a suitable IDE such as Xilinx.
top_hwx
- quartus 红外遥控接收解码工程以及相关代码。可直接使用-quartus ii hwx project and source code 毛can be directly used