资源列表
AD5623
- AD5623可编程基准源串行程序，还有波形测试截图-SPI for AD5623
uart_an_jian
- verilog描述的串口，能够接收数据，发送数据采用按键触发-Verilog descr iption of the serial port, receive data, send data using the trigger button
uart_8
- 用verilog描述的串口通信接口，主体为接收机和发送机两个模块-Serial communication interface with Verilog descr iption, subject to a receiver and transmitter module two
led
- LED呼吸灯硬件编程语言 Verilog 实现占空比变化LED灯缓慢点亮和熄灭的效果-LED Breathe
8B10B
- 以太网PHY层中的组成部分 8B10B编码器-Part of the Ethernet PHY layer in 8B10B encoder
lab28
- 采用5级流水线MIPS微处理器设计，实现32位流水线的算数、逻辑、以为等指令-pipeline MIPS
uart_fifo
- FPGA与PC的串口通信代码，使用了FIFO作为数据的缓存。-FPGA and PC serial communication code, use the FIFO as cached data.
clock
- 基于Verilog的多功能数字钟，看代码最好用quartus软件打开看。结合说明文档看。-Multi function digital clock based on Verilog, look at the code is best to use quartus software to open to see. Combined with the documentation see.
account
- 一个电话计费器程序的实例，里面有文档说明相关信号的定义。-An example of a telephone billing procedures, there is documentation of the definition of the relevant signal.
FIR
- 基于Verilog的FIR滤波器的设计，该代码包含完整的工程，可以利用quartus软件直接运行-Design of FIR filter based on Verilog, the code contains a complete project, can use quartus software to run directly
div_3
- 用Verilog实现时钟三分频，该代码包含完整的工程文件，可直接运行。-The realization of clock frequency of three Verilog, the code contains the complete engineering documents, can be directly run.
Posedge-Detection-Circuit
- Verilog脉冲边沿检查，此代码包含完整的工程，利用quartus软件可以直接运行仿真。-Verilog edge of pulse examination, this code contains the complete engineering, quartus software can be used to directly run the simulation.