资源列表
VHDL
- 先设计序列发生器产生序列：1011010001101010；再设计序列检测器，检测序列发生器产生序列，若检测到信号与预置待测信号相同，则输出“1”，否则输出“0”，并且将检测到的信号的显示出来。-First design sequence generator sequence: 1011010001101010 redesign sequence detector to detect sequence generator sequence, if the same signal is dete
LED
- FPGA驱动LED灯循环，代码简单，适合初学者，内有Modsim文件可直接进行仿真-FPGA-driven LED lights cycle, the code is simple, suitable for beginners, there Modsim files can be directly simulated
water_lamp
- 一个基于verilog的流水灯程序，一共有8个灯，到达边沿后自动返回，约束文件对应的是BASYS2的看法版-A water lamp procedures, based on verilog,
clk_div_N
- 程序可以实现时钟的任意偶数分频，使用Verilog语言编写。在quartus ii中得到验证并进行了仿真-Program can be any even divided clock using Verilog language. Been verified in quartus ii and simulation
wishbone_to_avalon
- wishbone-slave-and-master-to-avalon-bus,是关于wishbone总线和Avalon总线的转换，有实用价值，采用的是verilog编写
ROM_test
- 测试ROM的例子用Verilog写的，里面有测试文件，测试通过完全可用！-Examples of test ROM data
TEST
- 这是一段VHDL代码，用于对FPGA开发环境的熟悉。-This is a VHDL .
transport-light
- 提供利用FPGA设计一个简单交通灯的方法。提供原码以及逻辑图的文件-transport light
counterbasedDPWM
- 计数器方式的DPWM，有点简单，1本人是初学者，希望见谅，有更好的一定及时上传-DPWM Counter mode, a little simple, I am a beginner, I hope will forgive me, surely there is a better and timely uploads
adder_4
- 四位加法器的三种实现方法，包括行为级描述、行波进位加法器、超前进位加法器-Three of four adder implementations, including behavioral descr iptions, ripple carry adder, look-ahead adder
cpu_1
- 用verilog设计五级CPU的框架，需要自己另行补充指令，可作为学生作业和训练内容-Five CPU with verilog design framework, needs its own separate supplemental instruction can be used as student assignments and training content
Fisheye_Correction_v2
- 基于DE2-115的鱼眼畸变矫正verilog实现，具有拍照即存储照片功能，通过VGA输出实时的矫正后的图像-Based DE2-115 fisheye image distortion correction verilog realized that store photos with a camera function, real-time via the VGA output after correction