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- S963-AtvUdt S963方案SD卡的引导文件
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- p0302 istogram Equalization (a) Write a computer program for computing the histogram of an image. (b) Implement the histogram equalization technique discussed in Section 3.3.1. (c) Download Fig. 3.8(a) and perform histogram equalization on it. As a minimum
资源列表
08167129pllverilog
- PLL CONFIGUARTION USING FOAGA IN VERILOG LANGUAGE
7f8da115f83d72b263e5818b9374e466
- PLL configuration using FPGA IN VERILOG LANGUAGE FOR BEGINNER
方案二
- 本系统是基于CPLD和单片机的一种用于信号频率周期、时间间隔和占空比测量的数字频率计，系统由AGC（自动增益控制）电路、宽带放大电路、高速比较电路实现有效值10mV/频率100MHz和处理显示部分组成，其中AGC电路实现幅度自动增益控制使放大后的信号幅度在一定的范围内保持一致，比较电路将前级电路输出的信号转换成CPLD,利用等精度测频原理，实现闸门时间1S的高精度测量。单片机通信处理数据并显示，数据表明，系统精度达到发挥部分要求。(This system is a CPLD microcontr
9516
- 9516寄存器的配置，里面有详细英文备注，简单易懂，值得一看(9516 register configuration, there is a detailed English note, easy to understand, worth a look at)
Xilinx开发板初学者问题总结
- XILINX 系列FPGA开发过程中遇到的问题总结(Summary of problems encountered in the development of XILINX series FPGA)
VGA_Display
- 通过VGA实现图片的显示。代码可用，已通过验证。(The display of the picture is realized by VGA. The code is available and has been verified.)
UartSend
- 基于ACTEL的FPGA的串口发送驱动程序。(ACTEL based FPGA serial port driver.)
UartRecv
- 利用FPGA实现简单的串口接收驱动程序，actel。(Using FPGA to implement a simple serial port receiver driver, Actel)
FPGA设计指导原则
- FPGA设计的一般规则,可以用来做为入门手册。可以复活甲卡了圣诞节福利卡(FPGA infoormation fjkldasjflkafjdsklfaj jfdsklafj jfkladsjfl fjkalsd)
lab3
- lab 3 system generator : Signal Routing
lab2
- lab 2:Getting Started with Xilinx System Generator
E4_7_IIRCas
- 用vhdl语言在xilinx上实现的iir滤波器的设计(Design of IIR filter implemented on Xilinx in VHDL language)