资源列表
mj10
- 实现门禁系统，可以做网店实战的项目，对接数据库，不过里面没有数据库想对应的测试数据(The implementation of the entrance guard system, can do online shop actual projects, docking database, but there is no database to corresponding test data in it.)
《Verilog HDL设计与实战》配套代码(1)
- 《Verilog HDL设计与实战》配套代码 verilog源程序(Verilog HDL design and actual combat code Verilog source program)
DVCon_Europe_2015_T01_Presentation
- Advanced UVM Tutorial by Verilab
PPM
- 对4比特二进制数据进行PPM调制，位宽可修改(PPM modulation for 4 bit binary data)
verilab_dvcon2012_uvm_cooper
- Getting Started with UVM by Verilab
SystemVerilog_Synopsys
- systemverilog introduction by synopsys
ActelFPGA
- ACTEL FPGA system is introduced, the older the FPGA
alu
- Code to synthesize Arithmetic Logic Unit
MaxMovie 老干妈
- 演示demo 更清晰更明了 快速便捷 简洁。(The demo demo is clearer and clearer and faster and simpler.)
src
- v6 1x 3.125G rapidio协议工程代码(xilinx v6 rapidio data transmission protocol Practical project application engineering code)
v
- statistical signal processing,verilog
quartus和modelsim中使用mif和hex文件1
- quartus和modelsim中使用mif和hex文件1(fpga modelsim mif hex)