资源列表
异步FIFO
- 自己编写的同步和异步FIFO的verilog代码，验证过，有可靠性(Verilog code of my own synchronous and asynchronous FIFO, verified,and reliable.)
Q22-c.tar
- hdl design using verilog for beginer
Q4-b.tar
- beginer level verilog coding
Q4-a.tar
- verilog coding beginer level
Q3.tar
- hdl using verilog lenguage
Q2.tar
- vereilog design files for beginer
Q1.tar
- implementation of basic elecronics components using verilog HDL
Assignment-2.3.tar
- HDL code using verilog
Assignment-2.2.tar
- verilog-HDL codes for different basic digital circuits elements
Assignment-2.1.tar
- verilog codes for different basic digital circuits elements new
Assignment-1.3.tar
- verilog codes for different basic digital circuits elements
exp_fft_test_724
- 在quartus软件中调用FFT的IP核，编辑IP核的驱动模块，使得IP核读入数据进行处理，输出数据。使用modelsim进行联合仿真。(In the quartus software, the IP kernel of FFT is called, and the driver module of the IP kernel is edited, so that the IP kernel is read into the data for processing and output data