资源列表
daojishi
- 基于VHDL编写的60S倒计时，可以设置倒计时开始时间， 重置倒计时，倒计时结束数码管会闪烁，蜂鸣器报警，quartus软件亲测可用。-60S-based VHDL, countdown, countdown start time can be set, reset the countdown, countdown to the end of the LED will blink, buzzer alarm, quartus software pro-test available.
huxi
- 基于VHDL设计四个频率不同的呼吸灯，呼吸频率分别为 0.1Hz,0.2Hz，0.4Hz，0.8Hz 呼吸灯原理：利用PWM波控制led的亮度，的 原始代码 quartus软件亲测可用。-VHDL-based design in four different frequencies breathing light, breathing frequency was 0.1Hz, 0.2Hz, 0.4Hz, 0.8Hz breathing light principle: the use PWM
fifo_env
- for synchronization when we are dealing with 2 different clock domain
zuoyepaoma2
- 基于FPGA的跑马灯设计，可实现一个灯独跑，两个灯连跑，间断跑，隔着2个灯跑自定义跑灯形式。quartus软件亲测可用，自己编写的~-Marquee FPGA-based design can achieve an independent running lights, two lights Lianpao, intermittent run, run across two lights running lights in the form of custom. quartus software
FPGA_QPSK_EXP
- Quartus编写的QPSK解调仿真模块，用于各个功能模块的硬件仿真使用，由VHDL语言编写，适合通信工程专业人士使用-Quartus simulation module written QPSK demodulation hardware emulation for various functional modules using VHDL language for communications engineering professionals use
fat32_2G
- DE2开发板上SD卡相关设计,感兴趣的可以下载哈！-DE2 development board SD card related design, interested can download Ha!
arbiter-design-and-verification
- design and verification of arbiter
ADCS5451A_Sample
- 用verilog语言实现的ADCS5451 AD转换芯片的控制与数据读取。-Using verilog language to achieve ADCS5451 AD converter chip control and data read.
fft256
- 利用FPGA ip核实现256点的FFT转换，用vhdL语言实现。-Use FPGA ip core to achieve the 256-point FFT conversion with vhdL language.
ads7890
- 用VHDL编写的读取AD装换芯片ads7890程序，加了一个LED显示。-Read AD using VHDL chip installed for ads7890 program, plus a LED display.
mult-64bit-booth.txt
- 64位booth乘法器，verilog HDL， zip文件，modelsim测试通过-64 booth multiplier, verilog HDL, zip files, modelsim test
Source-code-of-Intelligent-Controller
- Source Code of Traffic Light Controller