资源列表
uart_rx_unpacked_0225_b
- 实现串口接收解包功能，包括启动，停止，复位，链路检测，位置环参数设置等功能。-Serial reception unpack functions including start, stop, reset, link detection, position loop parameter settings and other functions.
ADS1271
- VHDL的接口程序 24-bit 105ksps ADC 型号是：ADS1271 绝对稳定-VHDL interface program 24-bit 105ksps ADC models are: ADS1271 absolutely stable
VGA_NEW
- VGA显示，黑金动力社区的例子，有很好的学习意义-VGA display, an example of the power of black gold community, have a good sense of learning
wishbone-flash-
- wishbone总线的Flash闪存接口设计的相关资料-relevant information wishbone bus Flash memory interface design
Wishbone
- wishbone总线的一些研究，包括一些代码-wishbone verilog
DENG-JING-DU
- 基于FPGA的等精度频率计设计，实现百万分之一的误差精度-FPGA-based design and other precision frequency to achieve the accuracy of one millionth of error
CPU_MODEL
- implementation of CPU model using verilog
mux3_if_else
- implementation of multiplexer using if else statement in verilog
mux3_case
- implementation of multiplexer using case statements in verilog
mux_3_conditional
- implementation of multiplexer using conditional operator
counter7
- 4bit counter in verilog
Johnson_counter
- 基于FPGA的Jhonson计数器，能用按键控制流水灯-FPGA-based Jhonson counter, can control buttons light water