资源列表
WROM
- Twiddle factors in ROM
WDDRGEN
- Address generation for twiddle factors
CM_WADDR
- Complex multiplier with twiddle factor
CM
- Verilog Implementation of Complex Mutliplier
r22sdf_bf1
- Verilog Implementation of Butterfly 1 of R22SDF algorithm
10-sequence-detector
- 本系统采用实验箱的48MHz时钟作为输入时钟，将其分频得到计数器计数频率和序列检测器检测序列频率-The system uses a 48MHz clock experimental box as the input clock, to get the counter frequency divider and serial sequence frequency detector
sp601_sayac_sysgen_OK
- This a counter project for simulink using system generator blocks. There is LED output. I implemented it on spartan sp601 development board and it works.
evodem_mppt_son_hali_OK
- This my complete simulink project using xilinx system generator blocks. There is a buck converter and a control unit for FPGA calculating MPPT to get maximum power from the PV panel. MPPT calculation is done using sysgen blocks. Also HWCOSI
s3esk_picoblaze_amplifier_and_adc_control
- picoblaze amplifier and adc LTC1407A-1 control
s3esk_picoblaze_dac_control
- picoblaze DAC control spartan 3e
SineWAve
- xilinx system generator DAC simulink system code for black box
simu01
- spartan 3 series ADC vhdl code testbench