资源列表
zifu
- 关于用vga显示字符的一段程序，verilog-this code is about the display of Character
led_flow
- verilog 控制灯的闪烁，运用状态机写的-this code is about the Flicker of light
src1
- 关于串口通信的一段源代码， 希望能有帮助-this source code is about Serial communication
src
- VGA条形图案的显示，用verilog写的-this Source code is about the display of Stripe pattern
vhdl-all-english
- A major obstacle that stands in the way of efficient test response compaction are the unknown values (x-values) captured by scan cells during testing. If test responses with s and the correctness of the compactor inputs cannot be verified at
vhtoverilog
- A major obstacle of thge code is to convert verilog to convert an vhdl code that stands in the way of efficient test response compaction are the unknown values (x-values) captured by scan cells during testing. If test responses with x-values ar
source
- A major obstacle that stands in the way of efficient test response compaction are the unknown values (x-values) captured by scan cells during testing. If test responses with x-values are compacted, some of the outputs of the compactor may als
upload
- A major obstacle that stands in the way of efficient test response compaction are the unknown values (x-values) captured by scan cells during testing. If test responses with x-values are compacted, some of the outputs of the compactor may als
handbook
- Abstract—This paper presents a Viterbi-based test compression algorithm/architecture that provides high encoding efficiency and scalability with respect to the number of test channels. The proposed scheme finds a set of compressed test vectors
hierarchical-code
- Abstract—This paper presents a highly effective compactor architecture for processing test responses with a high percentage of x-values. The key component is a hierarchical configurable masking register, which allows the compactor to dynamically ad
myfir
- VHDL设计的FIR滤波器，有Matlab设计文件，Quartus II工程以及Modelsim仿真结果和说明文件-VHDL design FIR filters, Matlab design documents, Quartus II project and Modelsim simulation results and documentation
cam_generic_8s
- verilog 开发实例 无线通 信网络-verilog examples of the development of wireless communication networks