资源列表
MCS51_cpld
- VHDL语言编写的cpld与51单片机总线通信程序。结果应用证明。-VHDL language of the CPLD and 51 microcontroller bus communication program. Application results prove.
CPLD-CHABU
- 基于cpld 平台，VHDL语言编写，四轴两插补控制程序。包括单轴运动、两轴插补程序、CPLD与ARM通信程序。经过工程实践应用。-Based on the CPLD platform, VHDL language, four two axis interpolation control program. Including the single axis motion, two axis interpolation procedures, CPLD and ARM communication
MAX121_test
- max121，ad采集芯片，spi接口，fpga测试逻辑，verilog语言-max121, ad capture chip, spi interfaces, fpga test logic, verilog language
pci_test_altera
- pci接口测试，请用quartus12.0打开，否则注释乱码，代码没问题-pci interface testing, please use quartus12.0 open, otherwise garbled notes, code no problem
fpga_49
- pci接口 spi接口 和 uart接口数据传输 sopc挂载 verilog语言编写-pci interface spi and uart interface data transfer interfaces sopc mount verilog language
RS-422standardmodulev2
- rs422标准通讯模块 异步收发 verilog语言编写-rs422 standard communication module asynchronous receiver verilog language
Creating-Project-and-IP-Core-in-ISE
- 本文介绍了在ISE环境中如何新建工程，并且定义设置IP核进行开发-This article describes how new construction ISE environment, and define the settings IP core development
kc705-pcie-rdf0187-2013.2-c
- 基于KC705开发板的PCIE验证程序，用户在设计开发其他PCIE相关程序时可以参考-PCIE development board based KC705 verification process, users in the design and development of other related procedures can refer PCIE
ml605_PCIe_Gen1_x8_rdf0008_13.2_c
- 基于ML605开发板生成的x8 PCIE验证程序，可在ISE 13.2上正常运行，用户可根据自身需求进行修改-ML605 development board based on the generated x8 PCIE verification process can be run properly in ISE 13.2, the user can modify according to their needs
bmd_design
- 基于XILINX VC6LX550T FPGA开发的xapp1052即DMA传输验证程序，接口部分的管脚绑定可根据自身芯片型号进行修改-Verify that the DMA transfer process, pin binding interface part can be modified based on XILINX VC6LX550T FPGA development according to its own chip models xapp1052
cheng
- 开放式实验，CPU的设计，乘法器实验，简单乘法器-Open experiment, CPU design, the multiplier experiment, a simple multiplier
chufa
- 开放式实验，CPU实验除法器，一个简单的除法器-Open experiment, CPU test divider, a simple divider