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文件名称:AND_GATE

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2013-11-21
  • 文件大小：
    366.49kb
  • 已下载：
    0次
  • 提 供 者：
    a**
  • 相关连接：
    无
  • 下载说明：
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

执行“与”运算的基本门电路。有几个输入端，只有一个输出端。当所有的输入同时为“1”电平时，输出才为“1”电平，否则输出为“0”电平。-Perform basic gate "and" operation. There are several input, there is only one output. When all the input for the "1" at ordinary times at the same time, the output for a "1" level, otherwise output for the "0" level.
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下载文件列表

Project/and_gate.asm.rpt
Project/and_gate.done
Project/and_gate.dpf
Project/and_gate.fit.rpt
Project/and_gate.fit.smsg
Project/and_gate.fit.summary
Project/and_gate.flow.rpt
Project/and_gate.map.rpt
Project/and_gate.map.summary
Project/and_gate.pin
Project/and_gate.pof
Project/and_gate.qpf
Project/and_gate.qsf
Project/and_gate.sof
Project/and_gate.tan.rpt
Project/and_gate.tan.summary
Project/db/and_gate.(0).cnf.cdb
Project/db/and_gate.(0).cnf.hdb
Project/db/and_gate.asm.qmsg
Project/db/and_gate.asm_labs.ddb
Project/db/and_gate.cbx.xml
Project/db/and_gate.cmp.bpm
Project/db/and_gate.cmp.cdb
Project/db/and_gate.cmp.ecobp
Project/db/and_gate.cmp.hdb
Project/db/and_gate.cmp.logdb
Project/db/and_gate.cmp.rdb
Project/db/and_gate.cmp.tdb
Project/db/and_gate.cmp0.ddb
Project/db/and_gate.cmp2.ddb
Project/db/and_gate.cmp_bb.cdb
Project/db/and_gate.cmp_bb.hdb
Project/db/and_gate.cmp_bb.logdb
Project/db/and_gate.cmp_bb.rcf
Project/db/and_gate.dbp
Project/db/and_gate.db_info
Project/db/and_gate.eco.cdb
Project/db/and_gate.fit.qmsg
Project/db/and_gate.hier_info
Project/db/and_gate.hif
Project/db/and_gate.map.bpm
Project/db/and_gate.map.cdb
Project/db/and_gate.map.ecobp
Project/db/and_gate.map.hdb
Project/db/and_gate.map.logdb
Project/db/and_gate.map.qmsg
Project/db/and_gate.map_bb.cdb
Project/db/and_gate.map_bb.hdb
Project/db/and_gate.map_bb.logdb
Project/db/and_gate.pre_map.cdb
Project/db/and_gate.pre_map.hdb
Project/db/and_gate.psp
Project/db/and_gate.pss
Project/db/and_gate.rpp.qmsg
Project/db/and_gate.rtlv.hdb
Project/db/and_gate.rtlv_sg.cdb
Project/db/and_gate.rtlv_sg_swap.cdb
Project/db/and_gate.sgate.rvd
Project/db/and_gate.sgate_sm.rvd
Project/db/and_gate.sgdiff.cdb
Project/db/and_gate.sgdiff.hdb
Project/db/and_gate.signalprobe.cdb
Project/db/and_gate.sld_design_entry.sci
Project/db/and_gate.sld_design_entry_dsc.sci
Project/db/and_gate.syn_hier_info
Project/db/and_gate.tan.qmsg
Project/db/and_gate.tis_db_list.ddb
Project/db/prev_cmp_and_gate.map.qmsg
Project/db/prev_cmp_and_gate.qmsg
Project/Project/and_gate.asm.rpt
Project/Project/and_gate.done
Project/Project/and_gate.dpf
Project/Project/and_gate.fit.rpt
Project/Project/and_gate.fit.smsg
Project/Project/and_gate.fit.summary
Project/Project/and_gate.flow.rpt
Project/Project/and_gate.map.rpt
Project/Project/and_gate.map.summary
Project/Project/and_gate.pin
Project/Project/and_gate.pof
Project/Project/and_gate.qpf
Project/Project/and_gate.qsf
Project/Project/and_gate.sof
Project/Project/and_gate.tan.rpt
Project/Project/and_gate.tan.summary
Project/Project/db/and_gate.(0).cnf.cdb
Project/Project/db/and_gate.(0).cnf.hdb
Project/Project/db/and_gate.asm.qmsg
Project/Project/db/and_gate.asm_labs.ddb
Project/Project/db/and_gate.cbx.xml
Project/Project/db/and_gate.cmp.bpm
Project/Project/db/and_gate.cmp.cdb
Project/Project/db/and_gate.cmp.ecobp
Project/Project/db/and_gate.cmp.hdb
Project/Project/db/and_gate.cmp.logdb
Project/Project/db/and_gate.cmp.rdb
Project/Project/db/and_gate.cmp.tdb
Project/Project/db/and_gate.cmp0.ddb
Project/Project/db/and_gate.cmp2.ddb
Project/Project/db/and_gate.cmp_bb.cdb
Project/Project/db/and_gate.cmp_bb.hdb
Project/Project/db/and_gate.cmp_bb.logdb
Project/Project/db/and_gate.cmp_bb.rcf
Project/Project/db/and_gate.dbp
Project/Project/db/and_gate.db_info
Project/Project/db/and_gate.eco.cdb
Project/Project/db/and_gate.fit.qmsg
Project/Project/db/and_gate.hier_info
Project/Project/db/and_gate.hif
Project/Project/db/and_gate.map.bpm
Project/Project/db/and_gate.map.cdb
Project/Project/db/and_gate.map.ecobp
Project/Project/db/and_gate.map.hdb
Project/Project/db/and_gate.map.logdb
Project/Project/db/and_gate.map.qmsg
Project/Project/db/and_gate.map_bb.cdb
Project/Project/db/and_gate.map_bb.hdb
Project/Project/db/and_gate.map_bb.logdb
Project/Project/db/and_gate.pre_map.cdb
Project/Project/db/and_gate.pre_map.hdb
Project/Project/db/and_gate.psp
Project/Project/db/and_gate.pss
Project/Project/db/and_gate.rpp.qmsg
Project/Project/db/and_gate.rtlv.hdb
Project/Project/db/and_gate.rtlv_sg.cdb
Project/Project/db/and_gate.rtlv_sg_swap.cdb
Project/Project/db/and_gate.sgate.rvd
Project/Project/db/and_gate.sgate_sm.rvd
Project/Project/db/and_gate.sgdiff.cdb
Project/Project/db/and_gate.sgdiff.hdb
Project/Project/db/and_gate.signalprobe.cdb
Project/Project/db/and_gate.sld_design_entry.sci
Project/Project/db/and_gate.sld_design_entry_dsc.sci
Project/Project/db/and_gate.syn_hier_info
Project/Project/db/and_gate.tan.qmsg
Project/Project/db/and_gate.tis_db_list.ddb
Project/Project/db/prev_cmp_and_gate.map.qmsg
Project/Project/db/prev_cmp_and_gate.qmsg
Project/Project/RTL/and_gate.v
Project/RTL/and_gate.v
Project/Project/db
Project/Project/RTL
Project/db
Project/Project
Project/RTL
Project

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