文件名称:JPEG_Encode_verilog
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Verilog源代码,用来实现JPEG的编码
(系统自动生成,下载前可以参看下载内容)
下载文件列表
JPEG_Encode_verilog/dct/dct.v
JPEG_Encode_verilog/dct/dctu.v
JPEG_Encode_verilog/dct/dctub.v
JPEG_Encode_verilog/dct/dct_bench/bench_top.v
JPEG_Encode_verilog/dct/dct_cos_table.v
JPEG_Encode_verilog/dct/dct_mac.v
JPEG_Encode_verilog/dct/dct_syn.v
JPEG_Encode_verilog/dct/fdct.v
JPEG_Encode_verilog/dct/huffman/bench/bench_top.v
JPEG_Encode_verilog/dct/huffman/bench/generic_dpram.v
JPEG_Encode_verilog/dct/huffman/bench/generic_fifo_lfsr.v
JPEG_Encode_verilog/dct/huffman/bench/lfsr.v
JPEG_Encode_verilog/dct/huffman/bench/timescale.v
JPEG_Encode_verilog/dct/huffman/huffman_dec.v
JPEG_Encode_verilog/dct/huffman/huffman_enc.v
JPEG_Encode_verilog/dct/huffman/huffman_tables.v
JPEG_Encode_verilog/dct/ro_cnt.v
JPEG_Encode_verilog/dct/rtl_sim/Makefile.txt
JPEG_Encode_verilog/dct/ud_cnt.v
JPEG_Encode_verilog/dct/zigzag.v
JPEG_Encode_verilog/jpeg/bench_top/jpeg_encoder.v
JPEG_Encode_verilog/jpeg/jpeg_encoder.v
JPEG_Encode_verilog/jpeg/sim/cds.lib
JPEG_Encode_verilog/jpeg/sim/hdl.var
JPEG_Encode_verilog/jpeg/sim/Makefile.txt
JPEG_Encode_verilog/qnr/attic/div.v
JPEG_Encode_verilog/qnr/attic/div_us.v
JPEG_Encode_verilog/qnr/attic/ro_cnt.v
JPEG_Encode_verilog/qnr/attic/ud_cnt.v
JPEG_Encode_verilog/qnr/bench/bench_div_top.v
JPEG_Encode_verilog/qnr/bench/bench_qnr_top.v
JPEG_Encode_verilog/qnr/bench/timescale.v
JPEG_Encode_verilog/qnr/div_su.v
JPEG_Encode_verilog/qnr/div_uu.v
JPEG_Encode_verilog/qnr/jpeg_qnr.v
JPEG_Encode_verilog/rgb2ycrcb/modelsim.ini
JPEG_Encode_verilog/rgb2ycrcb/rgb2ycrcb/_info
JPEG_Encode_verilog/rgb2ycrcb/rgb2ycrcb.mpf
JPEG_Encode_verilog/rgb2ycrcb/rgb2ycrcb.v
JPEG_Encode_verilog/rgb2ycrcb/rgb2ycrcb_testbench.v
JPEG_Encode_verilog/rgb2ycrcb/rgb2ycrcb_webAddress.txt
JPEG_Encode_verilog/rgb2ycrcb/tcl_stacktrace.txt
JPEG_Encode_verilog/rgb2ycrcb/transcript
JPEG_Encode_verilog/rgb2ycrcb/work/_info
JPEG_Encode_verilog/run_length_coding/attic/jpeg_rle2.v
JPEG_Encode_verilog/run_length_coding/bench/bench.v.txt
JPEG_Encode_verilog/run_length_coding/jpeg_rle.v
JPEG_Encode_verilog/run_length_coding/jpeg_rle1.v
JPEG_Encode_verilog/run_length_coding/jpeg_rzs.v
JPEG_Encode_verilog/dct/huffman/bench
JPEG_Encode_verilog/dct/dct_bench
JPEG_Encode_verilog/dct/huffman
JPEG_Encode_verilog/dct/rtl_sim
JPEG_Encode_verilog/jpeg/bench_top
JPEG_Encode_verilog/jpeg/sim
JPEG_Encode_verilog/qnr/attic
JPEG_Encode_verilog/qnr/bench
JPEG_Encode_verilog/rgb2ycrcb/rgb2ycrcb
JPEG_Encode_verilog/rgb2ycrcb/work
JPEG_Encode_verilog/run_length_coding/attic
JPEG_Encode_verilog/run_length_coding/bench
JPEG_Encode_verilog/dct
JPEG_Encode_verilog/jpeg
JPEG_Encode_verilog/qnr
JPEG_Encode_verilog/rgb2ycrcb
JPEG_Encode_verilog/run_length_coding
JPEG_Encode_verilog
www.dssz.com.txt
JPEG_Encode_verilog/dct/dctu.v
JPEG_Encode_verilog/dct/dctub.v
JPEG_Encode_verilog/dct/dct_bench/bench_top.v
JPEG_Encode_verilog/dct/dct_cos_table.v
JPEG_Encode_verilog/dct/dct_mac.v
JPEG_Encode_verilog/dct/dct_syn.v
JPEG_Encode_verilog/dct/fdct.v
JPEG_Encode_verilog/dct/huffman/bench/bench_top.v
JPEG_Encode_verilog/dct/huffman/bench/generic_dpram.v
JPEG_Encode_verilog/dct/huffman/bench/generic_fifo_lfsr.v
JPEG_Encode_verilog/dct/huffman/bench/lfsr.v
JPEG_Encode_verilog/dct/huffman/bench/timescale.v
JPEG_Encode_verilog/dct/huffman/huffman_dec.v
JPEG_Encode_verilog/dct/huffman/huffman_enc.v
JPEG_Encode_verilog/dct/huffman/huffman_tables.v
JPEG_Encode_verilog/dct/ro_cnt.v
JPEG_Encode_verilog/dct/rtl_sim/Makefile.txt
JPEG_Encode_verilog/dct/ud_cnt.v
JPEG_Encode_verilog/dct/zigzag.v
JPEG_Encode_verilog/jpeg/bench_top/jpeg_encoder.v
JPEG_Encode_verilog/jpeg/jpeg_encoder.v
JPEG_Encode_verilog/jpeg/sim/cds.lib
JPEG_Encode_verilog/jpeg/sim/hdl.var
JPEG_Encode_verilog/jpeg/sim/Makefile.txt
JPEG_Encode_verilog/qnr/attic/div.v
JPEG_Encode_verilog/qnr/attic/div_us.v
JPEG_Encode_verilog/qnr/attic/ro_cnt.v
JPEG_Encode_verilog/qnr/attic/ud_cnt.v
JPEG_Encode_verilog/qnr/bench/bench_div_top.v
JPEG_Encode_verilog/qnr/bench/bench_qnr_top.v
JPEG_Encode_verilog/qnr/bench/timescale.v
JPEG_Encode_verilog/qnr/div_su.v
JPEG_Encode_verilog/qnr/div_uu.v
JPEG_Encode_verilog/qnr/jpeg_qnr.v
JPEG_Encode_verilog/rgb2ycrcb/modelsim.ini
JPEG_Encode_verilog/rgb2ycrcb/rgb2ycrcb/_info
JPEG_Encode_verilog/rgb2ycrcb/rgb2ycrcb.mpf
JPEG_Encode_verilog/rgb2ycrcb/rgb2ycrcb.v
JPEG_Encode_verilog/rgb2ycrcb/rgb2ycrcb_testbench.v
JPEG_Encode_verilog/rgb2ycrcb/rgb2ycrcb_webAddress.txt
JPEG_Encode_verilog/rgb2ycrcb/tcl_stacktrace.txt
JPEG_Encode_verilog/rgb2ycrcb/transcript
JPEG_Encode_verilog/rgb2ycrcb/work/_info
JPEG_Encode_verilog/run_length_coding/attic/jpeg_rle2.v
JPEG_Encode_verilog/run_length_coding/bench/bench.v.txt
JPEG_Encode_verilog/run_length_coding/jpeg_rle.v
JPEG_Encode_verilog/run_length_coding/jpeg_rle1.v
JPEG_Encode_verilog/run_length_coding/jpeg_rzs.v
JPEG_Encode_verilog/dct/huffman/bench
JPEG_Encode_verilog/dct/dct_bench
JPEG_Encode_verilog/dct/huffman
JPEG_Encode_verilog/dct/rtl_sim
JPEG_Encode_verilog/jpeg/bench_top
JPEG_Encode_verilog/jpeg/sim
JPEG_Encode_verilog/qnr/attic
JPEG_Encode_verilog/qnr/bench
JPEG_Encode_verilog/rgb2ycrcb/rgb2ycrcb
JPEG_Encode_verilog/rgb2ycrcb/work
JPEG_Encode_verilog/run_length_coding/attic
JPEG_Encode_verilog/run_length_coding/bench
JPEG_Encode_verilog/dct
JPEG_Encode_verilog/jpeg
JPEG_Encode_verilog/qnr
JPEG_Encode_verilog/rgb2ycrcb
JPEG_Encode_verilog/run_length_coding
JPEG_Encode_verilog
www.dssz.com.txt
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